Hi Miles,
Thank you for the patch! Perhaps something to improve:
[auto build test WARNING on joro-iommu/next]
[also build test WARNING on v5.18-rc3 next-20220422]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--bas
On 2022/4/23 13:14, Christoph Hellwig wrote:
On Sat, Apr 23, 2022 at 10:04:39AM +0800, Lu Baolu wrote:
The generic_iommu_put_resv_regions() itself is a callback. Why bothering
adding another callback from the same iommu driver in it? Or, you are
going to remove the put_resv_regions from the iomm
Looks good:
Reviewed-by: Christoph Hellwig
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On Sat, Apr 23, 2022 at 10:04:39AM +0800, Lu Baolu wrote:
> The generic_iommu_put_resv_regions() itself is a callback. Why bothering
> adding another callback from the same iommu driver in it? Or, you are
> going to remove the put_resv_regions from the iommu ops?
It is a driver method, but these r
On 2022/4/23 00:28, Shameer Kolothum via iommu wrote:
diff --git a/drivers/iommu/iommu.c b/drivers/iommu/iommu.c
index f2c45b85b9fc..ffcfa684e80c 100644
--- a/drivers/iommu/iommu.c
+++ b/drivers/iommu/iommu.c
@@ -2597,16 +2597,22 @@ void iommu_put_resv_regions(struct device *dev, struct
list_hea
When larbdev is NULL (in the case I hit, the node is incorrectly set
iommus = <&iommu NUM>), it will cause device_link_add() fail and
the kernel crashes when we try to print dev_name(larbdev).
Fix it by adding a NULL pointer check before
device_link_add/device_link_remove.
It should work for norm
On 2022-04-22 21:06, Alex Deucher wrote:
Add preliminary documentation for AMD IOMMU and combine
with the existing Intel IOMMU documentation and clean
up and modernize some of the existing documentation to
align with the current state of the kernel.
FWIW,
Reviewed-by: Robin Murphy
Signed-of
On Thu, Apr 21, 2022 at 9:42 AM Christoph Hellwig wrote:
> arm is the last platform not using the dma-direct code for directly
> mapped DMA. With the dmaboune removal from Arnd we can easily switch
> arm to always use dma-direct now (it already does for LPAE configs
> and nommu). I'd love to me
Add preliminary documentation for AMD IOMMU and combine
with the existing Intel IOMMU documentation and clean
up and modernize some of the existing documentation to
align with the current state of the kernel.
Signed-off-by: Alex Deucher
---
V2: Incorporate feedback from Robin to clarify IOMMU vs
[Public]
> -Original Message-
> From: Robin Murphy
> Sent: Friday, April 22, 2022 3:41 PM
> To: Deucher, Alexander ; linux-
> d...@vger.kernel.org; linux-ker...@vger.kernel.org; cor...@lwn.net;
> h...@zytor.com; x...@kernel.org; dave.han...@linux.intel.com;
> b...@alien8.de; mi...@redhat.
On 2022-04-22 18:54, Alex Deucher wrote:
[...]
+Intel Specific Notes
+
+
+Graphics Problems?
+^^
+
+If you encounter issues with graphics devices, you can try adding
+option intel_iommu=igfx_off to turn off the integrated graphics engine.
+If this fixes anythin
Add preliminary documentation for AMD IOMMU and combine
with the existing Intel IOMMU documentation and clean
up and modernize some of the existing documentation to
align with the current state of the kernel.
Signed-off-by: Alex Deucher
---
V2: Incorporate feedback from Robin to clarify IOMMU vs
[Public]
> -Original Message-
> From: Deucher, Alexander
> Sent: Friday, April 22, 2022 1:54 PM
> To: linux-...@vger.kernel.org; linux-ker...@vger.kernel.org;
> cor...@lwn.net; h...@zytor.com; x...@kernel.org;
> dave.han...@linux.intel.com; b...@alien8.de; mi...@redhat.com;
> t...@linutro
There's no need to show consumer side in provider examples. The ones
used here are undocumented or undocumented in schemas which results in
warnings.
Signed-off-by: Rob Herring
---
.../devicetree/bindings/iommu/mediatek,iommu.yaml | 10 --
.../devicetree/bindings/iommu/samsung,sysmm
On 2022-04-22 19:37, Krishna Reddy wrote:
Good effort to isolate bus config from smmu drivers.
Reviewed-By: Krishna Reddy
Thanks!
I have an orthogonal question here.
Can the following code handle the case, where different buses have different
type of SMMU instances(like one bus has SMMUv2 a
Good effort to isolate bus config from smmu drivers.
Reviewed-By: Krishna Reddy
I have an orthogonal question here.
Can the following code handle the case, where different buses have different
type of SMMU instances(like one bus has SMMUv2 and another bus has SMMUv3)?
If it need to handle the ab
Add preliminary documentation for AMD IOMMU and combine
with the existing Intel IOMMU documentation and clean
up and modernize some of the existing documentation to
align with the current state of the kernel.
Signed-off-by: Alex Deucher
---
V2: Incorporate feedback from Robin to clarify IOMMU vs
From: Jon Nettleton
Check if there is any RMR info associated with the devices behind
the SMMU and if any, install bypass SMRs for them. This is to
keep any ongoing traffic associated with these devices alive
when we enable/reset SMMU during probe().
Signed-off-by: Jon Nettleton
Signed-off-by:
Check if there is any RMR info associated with the devices behind
the SMMUv3 and if any, install bypass STEs for them. This is to
keep any ongoing traffic associated with these devices alive
when we enable/reset SMMUv3 during probe().
Signed-off-by: Shameer Kolothum
---
drivers/iommu/arm/arm-smm
By default, disable_bypass flag is set and any dev without
an iommu domain installs STE with CFG_ABORT during
arm_smmu_init_bypass_stes(). Introduce a "force" flag and
move the STE update logic to arm_smmu_init_bypass_stes()
so that we can force it to install CFG_BYPASS STE for specific
SIDs.
This
Introduce a helper to check the sid range and to init the l2 strtab
entries(bypass). This will be useful when we have to initialize the
l2 strtab with bypass for RMR SIDs.
Signed-off-by: Shameer Kolothum
---
drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 28 +++--
1 file changed,
This will provide a way for SMMU drivers to retrieve StreamIDs
associated with IORT RMR nodes and use that to set bypass settings
for those IDs.
Signed-off-by: Shameer Kolothum
---
drivers/acpi/arm64/iort.c | 28
include/linux/acpi_iort.h | 8
2 files chang
Currently IORT provides a helper to retrieve HW MSI reserve regions.
Change this to a generic helper to retrieve any IORT related reserve
regions. This will be useful when we add support for RMR nodes in
subsequent patches.
[Lorenzo: For ACPI IORT]
Reviewed-by: Lorenzo Pieralisi
Reviewed-by: Chri
Parse through the IORT RMR nodes and populate the reserve region list
corresponding to a given IOMMU and device(optional). Also, go through
the ID mappings of the RMR node and retrieve all the SIDs associated
with it.
Signed-off-by: Shameer Kolothum
---
drivers/acpi/arm64/iort.c | 290 ++
At present iort_iommu_msi_get_resv_regions() returns the number of
MSI reserved regions on success and there are no users for this.
The reserved region list will get populated anyway for platforms
that require the HW MSI region reservation. Hence, change the
function to return void instead.
Review
A callback is introduced to struct iommu_resv_region to free memory
allocations associated with the reserved region. This will be useful
when we introduce support for IORT RMR based reserved regions.
Signed-off-by: Shameer Kolothum
---
drivers/iommu/iommu.c | 16 +++-
include/linux/i
Hi
v9 --> v10
-Addressed Christoph's comments. We now have a callback to
struct iommu_resv_region to free all related memory and also dropped
the FW specific union and now has a container struct iommu_iort_rmr_data.
See patches #1 & #4
-Added R-by from Christoph.
-Dropped R-by from Loren
On Fri, Apr 22, 2022 at 09:15:01PM +0800, zhangfei@foxmail.com wrote:
> > I'm trying to piece together what happens from the kernel point of view.
> >
> > * master process with mm A opens a queue fd through uacce, which calls
> >iommu_sva_bind_device(dev, A) -> PASID 1
> >
> > * master fo
Release dma coherent memory before rvdev is free in
rproc_rvdev_release().
Below is the kmemleak report:
unreferenced object 0xff8051c1a980 (size 128):
comm "sh", pid 4895, jiffies 4295026604 (age 15481.896s)
hex dump (first 32 bytes):
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 .
Add dma_release_coherent_memory to DMA API to allow dma
user call it to release dev->dma_mem when the device is
removed.
Signed-off-by: Mark-PK Tsai
---
include/linux/dma-map-ops.h | 3 +++
kernel/dma/coherent.c | 10 --
2 files changed, 11 insertions(+), 2 deletions(-)
diff --gi
Release dma coherent memory before rvdev is free in
rproc_rvdev_release().
Below is the kmemleak report:
unreferenced object 0xff8051c1a980 (size 128):
comm "sh", pid 4895, jiffies 4295026604 (age 15481.896s)
hex dump (first 32 bytes):
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 .
Hi, Jean
On 2022/4/22 下午6:11, Jean-Philippe Brucker wrote:
On Fri, Apr 22, 2022 at 05:03:10PM +0800, zhangfei@foxmail.com wrote:
[...]
Have tested, still got some issue with our openssl-engine.
1. If openssl-engine does not register rsa, nginx works well.
2. If openssl-engine register rs
On 2022/4/22 11:05, Tian, Kevin wrote:
From: Lu Baolu
Sent: Thursday, April 21, 2022 7:36 PM
This field make the requests snoop processor caches irrespective of
other attributes in the request or other fields in paging structure
entries used to translate the request.
I think you want to first
On 2022/4/22 10:47, Tian, Kevin wrote:
From: Lu Baolu
Sent: Thursday, April 21, 2022 7:36 PM
The latest VT-d specification states that the PGSNP field in the pasid
table entry should be treated as Reserved(0) for implementations not
supporting Snoop Control (SC=0 in the Extended Capability Regis
On 2022/4/22 20:33, Robin Murphy wrote:
The ->probe_finalize hook only runs after ->probe_device succeeds,
so we can move that over to the new dev_iommu_ops() as well.
Signed-off-by: Robin Murphy
Reviewed-by: Lu Baolu
Best regards,
baolu
---
Another cheeky little one which doesn't need t
The ->probe_finalize hook only runs after ->probe_device succeeds,
so we can move that over to the new dev_iommu_ops() as well.
Signed-off-by: Robin Murphy
---
Another cheeky little one which doesn't need to wait...
drivers/iommu/iommu.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
Hi Joerg,
Unusually, we've got some SMMU driver fixes this time around. Summary in
the tag -- please can you pull these for 5.18?
Cheers,
Will
--->8
The following changes since commit 3123109284176b1532874591f7c81f3837bbdc17:
Linux 5.18-rc1 (2022-04-03 14:08:21 -0700)
are available in the
On Thu, 21 Apr 2022 13:45:04 +0530, Ashish Mhetre wrote:
> Tegra194 and Tegra234 SoCs have the erratum that causes walk cache
> entries to not be invalidated correctly. The problem is that the walk
> cache index generated for IOVA is not same across translation and
> invalidation requests. This is
On Fri, Apr 22, 2022 at 05:03:10PM +0800, zhangfei@foxmail.com wrote:
[...]
> > Have tested, still got some issue with our openssl-engine.
> >
> > 1. If openssl-engine does not register rsa, nginx works well.
> >
> > 2. If openssl-engine register rsa, nginx also works, but ioasid is not
> > f
Hi, Jean
On 2022/4/21 下午2:47, zhangfei@foxmail.com wrote:
On 2022/4/21 上午12:45, Jean-Philippe Brucker wrote:
Hi,
On Fri, Apr 15, 2022 at 02:51:08AM -0700, Fenghua Yu wrote:
From a6444e1e5bd8076f5e5c5e950d3192de327f0c9c Mon Sep 17 00:00:00 2001
From: Fenghua Yu
Date: Fri, 15 Apr 2022 0
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