On Thu, 28 Apr 2022 08:56:38 +0200
Krzysztof Kozlowski wrote:
Hi,
> On 27/04/2022 13:25, Andre Przywara wrote:
> > The Page Request Interface (PRI) is an optional PCIe feature. As such, a
> > SMMU would not need to handle it if the PCIe host bridge or the SMMU
> > itsel
nations of
wired interrupts, for instance just the "gerror" interrupt, or omitting
both "pri" and "cmdq-sync".
Signed-off-by: Andre Przywara
---
.../devicetree/bindings/iommu/arm,smmu-v3.yaml | 16 +++-
1 file changed, 11 insertions(+), 5 deletions(-
ght not be desired.
The Linux driver does not care about any order at all, just picks IRQs
based on their names, and treats all (wired) IRQs as optional.
Signed-off-by: Andre Przywara
---
.../bindings/iommu/arm,smmu-v3.yaml | 21 ++-
1 file changed, 16 insertions(+), 5
ed my Midway (the Highbank
successor) a bit with it (scp-ing GBs forth and back to a SATA SSD). Not a
really conclusive test, but so far it looks all fine.
So for the Highbank part:
Acked-by: Andre Przywara
Cheers,
Andre
> b/arch/arm/mach-mvebu/coherency.c|2
>
kernel build fails booting
(with the kernel DT), I'd like to see that merged.
Tested-by: Andre Przywara
Thanks,
Andre
> ---
> drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 15 +++
> 1 file changed, 15 insertions(+)
>
> diff --git a/drivers/iommu/arm/a
The Arm SMMUv1 DT binding only allows combining arm,mmu-401 with
arm,smmu-v1, even though the MMU-400 is compatible as well.
Allow this combination as well to let the Arm Juno board pass the test.
Signed-off-by: Andre Przywara
Acked-by: Robin Murphy
---
Documentation/devicetree/bindings/iommu
board pass the test.
Signed-off-by: Andre Przywara
---
Documentation/devicetree/bindings/iommu/arm,smmu.yaml | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml
b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml
index
(no MSIs).
Fixes: f6810c15cf973f ("iommu/arm-smmu: Clean up early-probing workarounds")
Signed-off-by: Andre Przywara
Acked-by: Robin Murphy
Reviewed-by: Eric Auger
---
drivers/vfio/vfio_iommu_type1.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/dr
(no MSIs).
Signed-off-by: Andre Przywara
---
Hi,
not sure this is the right fix, or we should rather check if the
platform doesn't support MSIs at all (which doesn't seem to be easy
to do).
Or is this because arm-smmu.c always reserves an IOMMU_RESV_SW_MSI
region?
Also this seems
On Fri, 28 Feb 2020 13:56:46 +
Will Deacon wrote:
> On Fri, Feb 28, 2020 at 01:42:54PM +0000, Andre Przywara wrote:
> > On Fri, 28 Feb 2020 10:50:25 +
> > Will Deacon wrote:
> > > On Fri, Feb 28, 2020 at 10:25:56AM +, Andre Przywara wrote:
> > >
On Fri, 28 Feb 2020 10:50:25 +
Will Deacon wrote:
> On Fri, Feb 28, 2020 at 10:25:56AM +0000, Andre Przywara wrote:
> > On Fri, 28 Feb 2020 10:04:47 +
> > Will Deacon wrote:
> >
> > Hi,
> >
> > > On Tue, Feb 25, 2020 at 04:01:54PM -0600, R
On Fri, 28 Feb 2020 10:04:47 +
Will Deacon wrote:
Hi,
> On Tue, Feb 25, 2020 at 04:01:54PM -0600, Rob Herring wrote:
> > On Tue, Feb 18, 2020 at 11:20 AM Will Deacon wrote:
> > >
> > > On Tue, Feb 18, 2020 at 11:13:16AM -0600, Rob Herring wrote:
> > > > Cc: Will Deacon
> > > > Cc: Robi
On Tue, 18 Feb 2020 11:13:10 -0600
Rob Herring wrote:
Hi,
> Calxeda has been defunct for 6 years now. Use of Calxeda servers carried
> on for some time afterwards primarily as distro builders for 32-bit ARM.
> AFAIK, those systems have been retired in favor of 32-bit VMs on 64-bit
> hosts.
>
>
e allocation and
> mapping calls directly as well. That way we can further streamline the
> helper back to exclusively operating on DMA domains.
>
> Fixes: b61d271e59d7 ("iommu/dma: Move domain lookup into
> __iommu_dma_{map,unmap}")
> Reported-by: Shameer Kolothum
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