Re: [PATCH v2 4/4] iommu: Prevent VMD child devices from being remapping targets

[+cc Robin] This series looks fine to me as far as PCI is concerned, and I'd be happy to take it via my tree given an ack from David for this IOMMU piece. Alternatively, you can add my Acked-by: Bjorn Helgaas <bhelg...@google.com> to the other patches if you want to take it via anothe

Re: [PATCH 1/3] MAINTAINERS: Add Jonathan Derrick as VMD maintainer

On Mon, Aug 07, 2017 at 01:57:11PM -0600, Jon Derrick wrote: > Add myself as VMD maintainer > > Signed-off-by: Jon Derrick Keith, I'm looking for an ack from you since you're currently listed in MAINTAINERS. > --- > MAINTAINERS | 1 + > 1 file changed, 1

Re: [PATCH 3/3] iommu: prevent VMD child devices from being remapping targets

On Mon, Aug 07, 2017 at 01:57:13PM -0600, Jon Derrick wrote: > VMD child devices must use the VMD endpoint's ID as the DMA source. > Because of this, there needs to be a way to link the parent VMD > endpoint's DMAR domain to the VMD child devices' DMAR domain such that > attaching and detaching

Re: [PATCH 2/3] pci: Generalize is_vmd behavior

On Mon, Aug 07, 2017 at 01:57:12PM -0600, Jon Derrick wrote: > Generalize is_vmd behavior to remove dependency on domain number > checking in pci quirks. > > Signed-off-by: Jon Derrick > --- > arch/x86/include/asm/pci.h | 8 +++- > arch/x86/pci/common.c | 2

Re: [PATCH kernel v4 4/6] iommu: Set PCI_BUS_FLAGS_MSI_REMAP on iommu driver initialization

[+cc Joerg, iommu] On Fri, Jun 30, 2017 at 12:24 AM, Alexey Kardashevskiy wrote: > From: Yongji Xie > > Some iommu drivers would be initialized after PCI device > enumeration. So PCI_BUS_FLAGS_MSI_REMAP would not be set > when probing PCI devices although

Re: [PATCH v7 2/3] PCI: Add support for PCI inbound windows resources

On Mon, May 22, 2017 at 11:39 AM, Oza Pawandeep wrote: > This patch adds support for inbound memory window > for PCI RC drivers. > > It defines new function pci_create_root_bus2 which > takes inbound resources as an argument and fills in the > memory resource to PCI internal

Re: [PATCH 0/2] Save and restore pci properties to support FLR

On Tue, May 30, 2017 at 09:25:47AM -0700, Ashok Raj wrote: > Resending Jean's patch so it can be included earlier than his large > SVM commits. Original patch https://patchwork.kernel.org/patch/9593891 > was ack'ed by Bjorn. Let's commit these separately since we need > functionality earlier. > >

Re: [PATCH 2/2] PCI: Save properties required to handle FLR for replay purposes.

On Tue, May 30, 2017 at 09:25:49AM -0700, Ashok Raj wrote: > From: CQ Tang <cq.t...@intel.com> > > Requires: https://patchwork.kernel.org/patch/9593891 > > > After a FLR, pci-states need to be restored. This patch saves PASID features > and PRI reqs cached. &g

Re: [PATCH 1/2] PCI: Save properties required to handle FLR for replay purposes.

On Tue, May 23, 2017 at 03:33:22PM -0500, Bjorn Helgaas wrote: > On Wed, May 10, 2017 at 11:39:02AM -0700, Ashok Raj wrote: > > From: CQ Tang <cq.t...@intel.com> > > > > Requires: https://patchwork.kernel.org/patch/9593891 > > I'm not sure what the statu

Re: [PATCH 1/2] PCI: Save properties required to handle FLR for replay purposes.

On Wed, May 10, 2017 at 11:39:02AM -0700, Ashok Raj wrote: > From: CQ Tang > > Requires: https://patchwork.kernel.org/patch/9593891 I'm not sure what the status of the patch above is. I acked it, but it's part of a 30-patch IOMMU series, so I expect it to be merged via an

Re: [PATCH v6 2/3] iommu/pci: reserve IOVA for PCI masters

On Tue, May 16, 2017 at 10:52:06AM +0530, Oza Pawandeep wrote: > this patch reserves the IOVA for PCI masters. > ARM64 based SOCs may have scattered memory banks. > such as iproc based SOC has > > <0x 0x8000 0x0 0x8000>, /* 2G @ 2G */ > <0x0008 0x8000 0x3 0x8000>, /*

Re: [PATCH v6 1/3] of/pci/dma: fix DMA configuration for PCI masters

On Tue, May 16, 2017 at 10:52:05AM +0530, Oza Pawandeep wrote: > current device framework and OF framework integration assumes s/current/The current/ > dma-ranges in a way where memory-mapped devices define their > dma-ranges. (child-bus-address, parent-bus-address, length). > >

Re: [PATCH 1/3] iommu: of: Fix check for returning EPROBE_DEFER

On Wed, May 17, 2017 at 05:00:07PM +0530, Sricharan R wrote: > Now with iommu probe deferral, we return -EPROBE_DEFER > for master's that are connected to an iommu which is not s/master's/masters/ s/iommu/IOMMU/ in your English text (changelogs and comments). That seems to be the convention,

Re: [PATCH v1] ACPI: Switch to use generic UUID API

m> > Cc: Ben Skeggs <bske...@redhat.com> > Cc: Benjamin Tissoires <benjamin.tissoi...@redhat.com> > Cc: Joerg Roedel <j...@8bytes.org> > Cc: Adrian Hunter <adrian.hun...@intel.com> > Cc: Yisen Zhuang <yisen.zhu...@huawei.com> > Cc: Bjorn Helgaas &

Re: [PATCH v5 2/2] PCI: quirks: Fix ThunderX2 dma alias handling

On Tue, Apr 25, 2017 at 8:03 AM, Jayachandran C <jn...@caviumnetworks.com> wrote: > On Fri, Apr 21, 2017 at 12:57:05PM -0500, Bjorn Helgaas wrote: >> I did notice that all the Root Port devices claim to *not* be connected to >> slots, which doesn't seem right. For example

Re: [PATCH v5 2/2] PCI: quirks: Fix ThunderX2 dma alias handling

On Fri, Apr 21, 2017 at 05:05:41PM +, Jayachandran C wrote: > On Fri, Apr 21, 2017 at 10:48:15AM -0500, Bjorn Helgaas wrote: > > On Mon, Apr 17, 2017 at 12:47 PM, Jayachandran C > > <jn...@caviumnetworks.com> wrote: > > > On Fri, Apr 14, 2017 at 09:00:0

Re: [PATCH v5 2/2] PCI: quirks: Fix ThunderX2 dma alias handling

On Mon, Apr 17, 2017 at 12:47 PM, Jayachandran C <jn...@caviumnetworks.com> wrote: > On Fri, Apr 14, 2017 at 09:00:06PM -0500, Bjorn Helgaas wrote: >> On Fri, Apr 14, 2017 at 4:06 PM, Jayachandran C >> <jn...@caviumnetworks.com> wrote: >> > On Thu, Apr 13, 201

Re: [PATCH v5 2/2] PCI: quirks: Fix ThunderX2 dma alias handling

On Wed, Apr 19, 2017 at 7:25 PM, Jon Masters wrote: > One additional footnote. I spent a bunch of time recently on my personal > Xeon systems walking through the PCIe topology and aligning on how to > advise the ARM server community proceed going forward. If you look at > how

Re: [PATCH v5 2/2] PCI: quirks: Fix ThunderX2 dma alias handling

On Mon, Apr 17, 2017 at 12:47 PM, Jayachandran C <jn...@caviumnetworks.com> wrote: > On Fri, Apr 14, 2017 at 09:00:06PM -0500, Bjorn Helgaas wrote: >> On Fri, Apr 14, 2017 at 4:06 PM, Jayachandran C >> <jn...@caviumnetworks.com> wrote: >> > On Thu, Apr 13, 201

Re: [PATCH v5 2/2] PCI: quirks: Fix ThunderX2 dma alias handling

On Fri, Apr 14, 2017 at 4:06 PM, Jayachandran C <jn...@caviumnetworks.com> wrote: > On Thu, Apr 13, 2017 at 07:19:11PM -0500, Bjorn Helgaas wrote: >> I tentatively applied both patches to pci/host-thunder for v4.12. >> >> However, I am concerned about the topology here:

Re: [PATCH v5 2/2] PCI: quirks: Fix ThunderX2 dma alias handling

I tentatively applied both patches to pci/host-thunder for v4.12. However, I am concerned about the topology here: On Thu, Apr 13, 2017 at 08:30:45PM +, Jayachandran C wrote: > On Cavium ThunderX2 arm64 SoCs (called Broadcom Vulcan earlier), the > PCI topology is slightly unusual. For a

Re: [PATCH v4 2/2] PCI: quirks: Fix ThunderX2 dma alias handling

On Wed, Apr 12, 2017 at 08:41:20PM +, Jayachandran C wrote: > On Wed, Apr 12, 2017 at 02:11:38PM -0500, Bjorn Helgaas wrote: > > On Wed, Apr 12, 2017 at 06:10:34PM +, Jayachandran C wrote: > > > On Wed, Apr 12, 2017 at 11:21:18AM -0500, Bjorn Helgaas wrote: > >

Re: [PATCH v4 2/2] PCI: quirks: Fix ThunderX2 dma alias handling

On Wed, Apr 12, 2017 at 06:10:34PM +, Jayachandran C wrote: > On Wed, Apr 12, 2017 at 11:21:18AM -0500, Bjorn Helgaas wrote: > > On Tue, Apr 11, 2017 at 03:27:02PM +, Jayachandran C wrote: > > > On Tue, Apr 11, 2017 at 08:41:25AM -0500, Bjorn Helgaas wrote:

Re: [PATCH v4 2/2] PCI: quirks: Fix ThunderX2 dma alias handling

On Tue, Apr 11, 2017 at 03:27:02PM +, Jayachandran C wrote: > On Tue, Apr 11, 2017 at 08:41:25AM -0500, Bjorn Helgaas wrote: > > [+cc Joerg] > > > > On Tue, Apr 11, 2017 at 07:10:48AM +, Jayachandran C wrote: > > > On Mon, Apr 10, 2017 at 08:28:47PM -0500, B

Re: [PATCH v4 0/2] Handle Cavium ThunderX2 PCI topology quirk

On Apr 11, 2017 8:48 AM, "Bjorn Helgaas" <helg...@kernel.org> wrote: [+cc David] I forgot to mention that I'm also hoping for an ack from David, since he's listed as the maintainer of the ThunderX drivers. Never mind this, Jon pointed out that ThunderX2 is different than

Re: [PATCH v4 0/2] Handle Cavium ThunderX2 PCI topology quirk

[+cc David] I forgot to mention that I'm also hoping for an ack from David, since he's listed as the maintainer of the ThunderX drivers. On Mon, Apr 03, 2017 at 01:15:02PM +, Jayachandran C wrote: > Hi Bjorn, Alex, > > Sending this again (with a trivial fix to author name), please review. >

Re: [PATCH v4 2/2] PCI: quirks: Fix ThunderX2 dma alias handling

[+cc Joerg] On Tue, Apr 11, 2017 at 07:10:48AM +, Jayachandran C wrote: > On Mon, Apr 10, 2017 at 08:28:47PM -0500, Bjorn Helgaas wrote: > > Hi Jayachandran, > > > > On Mon, Apr 03, 2017 at 01:15:04PM +, Jayachandran C wrote: > > > The Cavium ThunderX2 arm6

Re: Partial BAR Address Allocation

On Mon, Mar 06, 2017 at 12:04:39PM +0100, Joerg Roedel wrote: > On Wed, Feb 22, 2017 at 05:39:44PM -0600, Bjorn Helgaas wrote: > > [+cc Joerg, iommu list] > > > > On Wed, Feb 22, 2017 at 03:44:53PM -0500, Sinan Kaya wrote: > > > On 2/22/2017 1:44 PM, Bjorn Helgaas

Re: [RFC PATCH 19/30] PCI: Cache PRI and PASID bits in pci_dev

e for ATS. > > Signed-off-by: Jean-Philippe Brucker <jean-philippe.bruc...@arm.com> Acked-by: Bjorn Helgaas <bhelg...@google.com> > --- > drivers/pci/ats.c | 23 +++ > include/linux/pci.h | 2 ++ > 2 files changed, 25 insertions(+) > > diff

Re: [RFC PATCH 18/30] PCI: Make "PRG Response PASID Required" handling common

from amd_iommu into the PCI subsystem, > renaming it to something more consistent with the spec, and introducing > another obscure acronym to make it all fit. Maybe mention the acronym itelf and spell it out here? > Signed-off-by: Jean-Philippe Brucker <jean-philippe.bruc...@arm.co

Re: [RFC PATCH 03/30] PCI: Move ATS declarations outside of CONFIG_PCI

ONFIG_PCI_ATS in arm_smmu_enable_ats() ("[RFC PATCH 04/30] iommu/arm-smmu-v3: Add support for PCI ATS"), right? If you remove the #ifdef, we'll call pci_enable_ats(), and it will fail if !pdev->ats_cap. Acked-by: Bjorn Helgaas <bhelg...@google.com> > --- > include/linu

Re: Partial BAR Address Allocation

[+cc Joerg, iommu list] On Wed, Feb 22, 2017 at 03:44:53PM -0500, Sinan Kaya wrote: > On 2/22/2017 1:44 PM, Bjorn Helgaas wrote: > > There is no way for a driver to say "I only need this memory BAR and > > not the other ones." The reason is because the PCI_COMMAND_ME

Re: [PATCH V7 00/11] IOMMU probe deferral support

On Mon, Jan 23, 2017 at 09:48:02PM +0530, Sricharan R wrote: > This series calls the dma ops configuration for the devices > at a generic place so that it works for all busses. > The dma_configure_ops for a device is now called during > the device_attach callback just before the probe of the >

Re: [PATCH V7 06/11] of/acpi: Configure dma operations at probe time for platform/amba/pci bus devices

I based platform/amba/pci bus devices. > > Signed-off-by: Sricharan R <sricha...@codeaurora.org> Acked-by: Bjorn Helgaas <bhelg...@google.com> (drivers/pci part) > --- > [V6 .. V7] > * Updated the subject and commit log as per comments > > [V5 .. V6] >

Re: [PATCH V7 10/11] iommu/arm-smmu: Clean up early-probing workarounds

On Mon, Jan 23, 2017 at 09:48:12PM +0530, Sricharan R wrote: > From: Robin Murphy > > Now that the appropriate ordering is enforced via profe-deferral of s/profe-deferral/probe-deferral/ > masters in core code, rip it all out and bask in the simplicity. > > Acked-by:

Re: [PATCH V7 09/11] arm64: dma-mapping: Remove the notifier trick to handle early setting of dma_ops

On Mon, Jan 23, 2017 at 09:48:11PM +0530, Sricharan R wrote: > With arch_setup_dma_ops now being called late during device's probe after > the device's iommu is probed, the notifier trick required to handle the > early setup of dma_ops before the iommu group gets created is not > required. So

Re: [PATCH V7 07/11] iommu: of: Handle IOMMU lookup failure with deferred probing or error

On Mon, Jan 23, 2017 at 09:48:09PM +0530, Sricharan R wrote: > From: Laurent Pinchart > > Failures to look up an IOMMU when parsing the DT iommus property need to > be handled separately from the .of_xlate() failures to support deferred > probing. > >

Re: possible dmar_init_reserved_ranges() error

On Mon, Dec 19, 2016 at 03:20:44PM -0600, Bjorn Helgaas wrote: > Hi guys, > > I have some questions about dmar_init_reserved_ranges(). On systems > where CPU physical address space is not identity-mapped to PCI bus > address space, e.g., where the PCI host bridge windows have _TRA

Re: possible dmar_init_reserved_ranges() error

Hi Ashok, On Thu, Dec 22, 2016 at 03:45:08PM -0800, Raj, Ashok wrote: > Hi Bjorn > > None in the platform group say they know about this. So i'm fairly sure > we don't do that on Intel hardware (x86). I'm pretty sure there was once an x86 prototype for which PCI bus addresses were not

Re: possible dmar_init_reserved_ranges() error

On Thu, Dec 22, 2016 at 05:27:14PM +0100, Joerg Roedel wrote: > Hi Bjorn, > > On Mon, Dec 19, 2016 at 03:20:44PM -0600, Bjorn Helgaas wrote: > > I have some questions about dmar_init_reserved_ranges(). On systems > > where CPU physical address space is not identity-mapped t

possible dmar_init_reserved_ranges() error

Hi guys, I have some questions about dmar_init_reserved_ranges(). On systems where CPU physical address space is not identity-mapped to PCI bus address space, e.g., where the PCI host bridge windows have _TRA offsets, I'm not sure we're doing the right thing. Assume we have a PCI host bridge

Re: [PATCH 5/5] PCI: Balance ports to avoid ACS errata on Pericom switches

On Wed, Oct 26, 2016 at 12:01:40PM -0600, Alex Williamson wrote: > As described in the included code comment, this quirk is intended to > work around an errata in a variety of Pericom 4-lane, 3 and 4 port > PCIe 2.0 switches. The switches advertise ACS capabilities, but the > P2P Request

Re: [PATCH 2/5] PCI: Extract link speed & width retrieval from pcie_get_minimum_link()

On Wed, Oct 26, 2016 at 12:01:22PM -0600, Alex Williamson wrote: > Signed-off-by: Alex Williamson > --- > drivers/pci/pci.c | 26 -- > include/linux/pci.h |2 ++ > 2 files changed, 22 insertions(+), 6 deletions(-) > > diff --git

Re: [PATCH 1/5] PCI: Make pci_std_enable_acs() non-static

On Wed, Oct 26, 2016 at 12:01:16PM -0600, Alex Williamson wrote: > For use by quirks. > > Signed-off-by: Alex Williamson > --- > drivers/pci/pci.c |2 +- > include/linux/pci.h |1 + > 2 files changed, 2 insertions(+), 1 deletion(-) > > diff --git

Re: [PATCH 4/5] iommu: Move REQ_ACS_FLAGS out to header and rename

On Thu, Nov 10, 2016 at 01:27:13PM +0100, Joerg Roedel wrote: > On Wed, Oct 26, 2016 at 12:01:34PM -0600, Alex Williamson wrote: > > Allow other parts of the kernel to see which PCI ACS flags the IOMMU > > layer considers necessary for isolation. > > > > Signed-off-by: Alex Williamson

Re: [PATCH v2 1/2] PCI: Add PCI device flag PCI_DEV_FLAGS_DMA_ALIAS_ROOT

On Thu, Jun 23, 2016 at 01:04:01PM +0100, Robin Murphy wrote: > On 23/06/16 06:01, Jon Masters wrote: > >On 05/11/2016 10:26 AM, Robin Murphy wrote: > >>(I have no actual objection to this patch, though, and at this point > >>I'm just chucking ideas about). > > > >Can I ask what the next steps are

Re: [PATCH v2 2/2] PCI: Handle Broadcom Vulcan DMA alias calculation quirk

On Sun, May 08, 2016 at 03:03:21PM +0530, Jayachandran C wrote: > The Broadcom Vulcan PCI topology is slightly unusual, for a multi-node > system, it looks like: > > [bus 0] > | > +--[node 0 PCI bridge 0.0.0] > | | > |[bus 1] > | +---[SoC PCI

Re: [RFC PATCH v2 12/15] drivers: acpi: implement acpi_dma_configure

t; > Signed-off-by: Lorenzo Pieralisi <lorenzo.pieral...@arm.com> > Cc: Bjorn Helgaas <bhelg...@google.com> > Cc: Robin Murphy <robin.mur...@arm.com> > Cc: Tomasz Nowicki <t...@semihalf.com> > Cc: Joerg Roedel <j...@8bytes.org> > Cc: "Rafael J.

Re: [PATCH 2/5] iommu: Set PCI_BUS_FLAGS_MSI_REMAP if IOMMU have capability of IRQ remapping

On Wed, May 25, 2016 at 01:54:23PM +0800, Yongji Xie wrote: > On 2016/5/25 5:11, Bjorn Helgaas wrote: > >On Wed, Apr 27, 2016 at 08:43:27PM +0800, Yongji Xie wrote: > >>The capability of IRQ remapping is abstracted on IOMMU side on > >>some archs. There is a existin

Re: [PATCH 2/5] iommu: Set PCI_BUS_FLAGS_MSI_REMAP if IOMMU have capability of IRQ remapping

On Wed, Apr 27, 2016 at 08:43:27PM +0800, Yongji Xie wrote: > The capability of IRQ remapping is abstracted on IOMMU side on > some archs. There is a existing flag IOMMU_CAP_INTR_REMAP for this. > > To have a universal flag to test this capability for different > archs on PCI side, we set

Re: [PATCH 3/5] PCI: Set PCI_BUS_FLAGS_MSI_REMAP if MSI controller supports IRQ remapping

On Wed, Apr 27, 2016 at 08:43:28PM +0800, Yongji Xie wrote: > On ARM HW the capability of IRQ remapping is abstracted on > MSI controller side. MSI_FLAG_IRQ_REMAPPING is used to advertise > this [1]. > > To have a universal flag to test this capability for different > archs on PCI side, we set

Re: [PATCH 1/5] PCI: Add a new PCI_BUS_FLAGS_MSI_REMAP flag

On Wed, Apr 27, 2016 at 08:43:26PM +0800, Yongji Xie wrote: > We introduce a new pci_bus_flags, PCI_BUS_FLAGS_MSI_REMAP > which indicates all devices on the bus are protected by the > hardware which supports IRQ remapping(intel naming). This changelog is ambiguous. It's possible that there is

Re: [RFC PATCH 09/11] drivers: acpi: implement acpi_dma_configure

to use the newly introduced > acpi_dma_configure function, providing the same functionality > as of_dma_configure on ARM systems and leaving behaviour unchanged > for all other arches. > > Signed-off-by: Lorenzo Pieralisi <lorenzo.pieral...@arm.com> > Cc: Bjorn Helgaas <bh

Re: [PATCH v4 0/6] PCI: Support multiple DMA aliases

On Mon, Apr 11, 2016 at 11:38:28PM -0500, Bjorn Helgaas wrote: > On Wed, Feb 24, 2016 at 01:43:32PM -0600, Bjorn Helgaas wrote: > > This is a revision of Jacek's v3 posting: > > http://lkml.kernel.org/r/1454152012-46337-1-git-send-email-jacek.lawrynow...@intel.com > > &g

Re: [PATCH v4 0/6] PCI: Support multiple DMA aliases

On Wed, Feb 24, 2016 at 01:43:32PM -0600, Bjorn Helgaas wrote: > This is a revision of Jacek's v3 posting: > http://lkml.kernel.org/r/1454152012-46337-1-git-send-email-jacek.lawrynow...@intel.com > > The changes from v3 are: > > - Split into smaller patches for reviewability

Re: [PATCH v4 3/6] PCI: Add support for multiple DMA aliases

On Tue, Mar 15, 2016 at 07:48:17PM -0500, Bjorn Helgaas wrote: > On Mon, Mar 14, 2016 at 10:43:40PM +, David Woodhouse wrote: > > On Thu, 2016-02-25 at 08:38 -0600, Bjorn Helgaas wrote: > > > > > > >  /* > > > > - * Look for aliases to or

Re: [PATCH v4 3/6] PCI: Add support for multiple DMA aliases

On Mon, Mar 14, 2016 at 10:43:40PM +, David Woodhouse wrote: > On Thu, 2016-02-25 at 08:38 -0600, Bjorn Helgaas wrote: > > > > >  /* > > > - * Look for aliases to or from the given device for exisiting groups.  > > > The > > > - * dma_alia

Re: [PATCH v4 3/6] PCI: Add support for multiple DMA aliases

On Wed, Feb 24, 2016 at 01:44:06PM -0600, Bjorn Helgaas wrote: > From: Jacek Lawrynowicz <jacek.lawrynow...@intel.com> > > (Sorry, I should have copied this changelog in the patch; I copied this manually from your v3 posting): > This patch solves IOMMU support issues with PC

[PATCH v4 6/6] PCI: Squash pci_dev_flags to remove holes

From: Jacek Lawrynowicz After removing PCI_DEV_FLAGS_DMA_ALIAS_DEVFN, the (1 << 4) value was unused. Squash the other values so all the bits are adjacent. No functional change intended. (I'm not sure this is worth doing. We have 16 flag bits and we're not even

[PATCH v4 5/6] pci: Add DMA alias quirk for mic_x200_dma

From: Jacek Lawrynowicz MIC x200 NTB forwards PCIe traffic using multiple alien RID. They have to be added as aliases to the DMA device in order to allow buffer access when IOMMU is enabled. Signed-off-by: Jacek Lawrynowicz Acked-by:

[PATCH v4 4/6] PCI: Rename dma_alias_is_enabled() to pci_devs_are_dma_aliases()

This should be folded into the previous patch. I left it separate to show the interface difference more clearly. Also, pci_devs_are_dma_aliases() uses PCI internals (dma_alias_mask), so I think it should be in PCI code instead of in IOMMU code. That would mean both it and pci_add_dma_alias()

[PATCH v4 0/6] PCI: Support multiple DMA aliases

pci_devs - Rename dma_alias_is_enabled() to indicate PCI context The only remaining thing I want to sort out is the dma_alias_is_enabled() vs pci_for_each_dma_alias() question Alex raised. I'll respond to the relevant part of the patch in this series with my specific questions. --- Bjorn

[PATCH v4 1/6] PCI: Add pci_add_dma_alias() to abstract implementation

From: Jacek Lawrynowicz Add a pci_add_dma_alias() interface to encapsulate the details of adding an alias. No functional change intended. --- drivers/pci/pci.c| 14 ++ drivers/pci/pci.h|2 ++ drivers/pci/quirks.c | 19 +++

[PATCH v4 2/6] PCI: Move informational printk to pci_add_dma_alias()

From: Jacek Lawrynowicz One of the quirks that adds DMA aliases logs an informational message in dmesg. Move that to pci_add_dma_alias() so all users log the message consistently. No functional change intended (except extra message). --- drivers/pci/pci.c|

[PATCH v4 3/6] PCI: Add support for multiple DMA aliases

From: Jacek Lawrynowicz --- drivers/iommu/iommu.c | 17 ++--- drivers/pci/pci.c | 11 +-- drivers/pci/probe.c |1 + drivers/pci/search.c | 14 +- include/linux/pci.h |4 +--- 5 files changed, 30 insertions(+),

Re: AMD-Vi: Unable to write to IOMMU perf counter.

[+cc Joerg, iommu list] Hi Andreas, On Thu, Feb 04, 2016 at 03:53:20PM +0100, Andreas Hartmann wrote: > Hello! > > The following happens with Linux 4.4.1 during boot on an MSI A78M-E35 > board. Additionally, I attached the complete dmesg. Thanks a lot for the report! I cc'd some folks who

Re: [PATCH] iommu/vt-d: Add support for multiple DMA aliases

On Wed, Jan 13, 2016 at 1:28 PM, David Woodhouse wrote: > On Mon, 2016-01-11 at 14:20 +0100, Jacek Lawrynowicz wrote: >> This patch solves IOMMU support issues with PCIe non-transparent bridges >> that use Requester ID look-up tables (LUT), e.g. PEX8733. Before exiting >> the

Re: Fwd: SWIOTLB on 32-bit PAE.

[+cc Konrad, Joerg, iommu list] On Fri, Oct 02, 2015 at 04:20:16PM +0200, Christian Melki wrote: > I discovered a strange error on my machine. 32-bit PAE 4.2.0 without > IOMMU code (yeah, I know). > When writing to an ext4 filesystem on a USB disk my kernel would hang > and not return control to

Re: [PATCH 10/22] PCI: Add pci_resource_to_peer()

On Tue, Sep 15, 2015 at 12:10:55PM -0500, Will Davis wrote: > Add helper to convert a struct resource to a peer DMA address. > > Signed-off-by: Will Davis > --- > include/linux/pci.h | 16 > 1 file changed, 16 insertions(+) > > diff --git

Re: [PATCH 09/22] PCI: Add pci_peer_traffic_supported()

On Tue, Sep 15, 2015 at 12:10:54PM -0500, Will Davis wrote: > Add checks for topology and ACS configuration to determine whether or not > peer traffic should be supported between two PCI devices. > > Signed-off-by: Will Davis > --- > drivers/pci/pci.c | 99 >

Re: [PATCH 00/22] DMA-API/PCI map_peer_resource support for peer-to-peer

Hi Will, On Tue, Sep 15, 2015 at 12:10:45PM -0500, Will Davis wrote: > Hi, > > This is the sixth version of a patchset to add the DMA APIs necessary to > map and unmap a PCI device's BAR to and from another PCI device's IOVA > domain. This enables PCI peer-to-peer traffic on x86 platforms where

[PATCH v3 10/11] PCI: Stop caching ATS Invalidate Queue Depth

Stop caching the Invalidate Queue Depth in struct pci_dev. pci_ats_queue_depth() is typically called only once per device, and it returns a fixed value per-device, so callers who need the value frequently can cache it themselves. Signed-off-by: Bjorn Helgaas bhelg...@google.com Reviewed-by: Joerg

[PATCH v3 02/11] PCI: Allocate ATS struct during enumeration

. Link: http://permalink.gmane.org/gmane.linux.kernel.iommu/9433 Reported-by: Gregor Dick gd...@solarflare.com Signed-off-by: Bjorn Helgaas bhelg...@google.com Reviewed-by: Joerg Roedel jroe...@suse.de --- drivers/pci/ats.c | 98 --- drivers/pci

[PATCH v3 03/11] PCI: Embed ATS info directly into struct pci_dev

The pci_ats struct is small and will get smaller, so I don't think it's worth allocating it separately from the pci_dev struct. Embed the ATS fields directly into struct pci_dev. Signed-off-by: Bjorn Helgaas bhelg...@google.com Reviewed-by: Joerg Roedel jroe...@suse.de --- drivers/pci/ats.c

[PATCH v3 00/11] PCI: Fix ATS deadlock

of how many associated VFs have ATS enabled - Add comment that ATS must be enabled on PF before on VFs - Require ATS to be disabled on all VFs and PF before changing STU --- Bjorn Helgaas (11): iommu/vt-d: Cache PCI ATS state and Invalidate Queue Depth PCI: Allocate ATS struct during

[PATCH v3 04/11] PCI: Reduce size of ATS structure elements

The extended capabilities list is linked with 12-bit pointers, and the ATS Smallest Translation Unit and Invalidate Queue Depth fields are both 5 bits. Use u16 and u8 to hold the extended capability address and the stu and qdep values. No functional change. Signed-off-by: Bjorn Helgaas bhelg

[PATCH v3 01/11] iommu/vt-d: Cache PCI ATS state and Invalidate Queue Depth

struct. This is similar to what amd_iommu.c does. Signed-off-by: Bjorn Helgaas bhelg...@google.com --- drivers/iommu/intel-iommu.c | 28 ++-- 1 file changed, 18 insertions(+), 10 deletions(-) diff --git a/drivers/iommu/intel-iommu.c b/drivers/iommu/intel-iommu.c index

[PATCH v3 07/11] PCI: Use pci_physfn() rather than looking up physfn by hand

Use the pci_physfn() helper rather than looking up physfn by hand. No functional change. Signed-off-by: Bjorn Helgaas bhelg...@google.com Reviewed-by: Joerg Roedel jroe...@suse.de --- drivers/pci/ats.c |8 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/pci

[PATCH v3 11/11] PCI: Remove pci_ats_enabled()

Remove pci_ats_enabled(). There are no callers outside the ATS code itself. We don't need to check ats_cap, because if we don't find an ATS capability, we'll never set ats_enabled. Signed-off-by: Bjorn Helgaas bhelg...@google.com Reviewed-by: Joerg Roedel jroe...@suse.de --- drivers/pci/ats.c

[PATCH v3 05/11] PCI: Rationalize pci_ats_queue_depth() error checking

We previously returned -ENODEV for devices that don't support ATS (except that we always returned 0 for VFs, whether or not they support ATS). For consistency, always return -EINVAL (not -ENODEV) if the device doesn't support ATS. Return zero for VFs that support ATS. Signed-off-by: Bjorn

[PATCH v3 09/11] PCI: Move ATS declarations to linux/pci.h so they're all together

Move ATS declarations to linux/pci.h so they're all in one place. Signed-off-by: Bjorn Helgaas bhelg...@google.com Reviewed-by: Joerg Roedel jroe...@suse.de --- include/linux/pci-ats.h | 41 - include/linux/pci.h | 10 +- 2 files changed, 9

[PATCH v3 08/11] PCI: Clean up ATS error handling

these error paths. Signed-off-by: Bjorn Helgaas bhelg...@google.com --- drivers/pci/ats.c | 11 ++- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/drivers/pci/ats.c b/drivers/pci/ats.c index 0b5b0ed..0f05274 100644 --- a/drivers/pci/ats.c +++ b/drivers/pci/ats.c @@ -44,11 +44,13

Re: [PATCH v4 10/12] pci: add pci_find_common_upstream_dev()

On Wed, Jul 22, 2015 at 04:39:55PM -0500, Will Davis wrote: Adds an interface to find the first device which is upstream of both devices. Signed-off-by: Will Davis wda...@nvidia.com --- drivers/pci/search.c | 25 + include/linux/pci.h | 2 ++ 2 files changed, 27

Re: [PATCH v4 07/12] pci: expose pci_find_host_bridge()

On Wed, Jul 22, 2015 at 04:39:52PM -0500, Will Davis wrote: This function takes a struct pci_bus * and returns the associated struct pci_host_bridge * upstream. Nits: for the PCI parts, please run git log --oneline and make yours match the style of the previous history. Same for the changelog

Re: [PATCH v2 00/11] PCI: Fix ATS deadlock

On Thu, Aug 06, 2015 at 06:06:34PM -0700, Yinghai Lu wrote: On Thu, Aug 6, 2015 at 9:03 AM, Yinghai Lu ying...@kernel.org wrote: On Wed, Jul 29, 2015 at 9:07 AM, Bjorn Helgaas bhelg...@google.com wrote: Bjorn Helgaas (11): iommu/vt-d: Cache PCI ATS state and Invalidate Queue Depth

Re: [PATCH v4 09/12] iommu/vt-d: implement (un)map_peer_resource

On Wed, Jul 22, 2015 at 04:39:54PM -0500, Will Davis wrote: Implement 'map_peer_resource' for the Intel IOMMU driver. Simply translate the resource to a physical address and route it to the same handlers used by the 'map_page' API. This allows a device to map another's resource, to enable

Re: [PATCH v2 00/11] PCI: Fix ATS deadlock

On Mon, Jul 20, 2015 at 07:13:49PM -0500, Bjorn Helgaas wrote: Gregor reported a deadlock [1] when enabling a VF that supports ATS. This series is intended to fix that. The second patch should be enough to fix the deadlock; the rest are simplification and cleanup. These are based on v4.2

Re: [PATCH v2 01/11] iommu/vt-d: Cache PCI ATS state and Invalidate Queue Depth

Hi Joerg, Thanks for all your help reviewing this! On Mon, Jul 27, 2015 at 03:08:10PM +0200, Joerg Roedel wrote: On Mon, Jul 20, 2015 at 07:13:57PM -0500, Bjorn Helgaas wrote: We check the ATS state (enabled/disabled) and fetch the PCI ATS Invalidate Queue Depth in performance-sensitive

Re: Since Linux 4.1: A lot of AMD-Vi IO_PAGE_FAULTs

[+cc Tejun, linux-ide] On Thu, Jul 23, 2015 at 11:22 PM, Andreas Hartmann andihartm...@freenet.de wrote: On Tue, Jul 21, 2015 at 06:35PM +0200, Joerg Roedel wrote: On Tue, Jul 21, 2015 at 06:20:23PM +0200, Andreas Hartmann wrote: [ 48.193901] 6[fglrx] Firegl kernel thread PID: 1840 [

[PATCH v2 11/11] PCI: Remove pci_ats_enabled()

Remove pci_ats_enabled(). There are no callers outside the ATS code itself. We don't need to check ats_cap, because if we don't find an ATS capability, we'll never set ats_enabled. Signed-off-by: Bjorn Helgaas bhelg...@google.com --- drivers/pci/ats.c |6 +++--- include/linux/pci.h

[PATCH v2 10/11] PCI: Stop caching ATS Invalidate Queue Depth

Stop caching the Invalidate Queue Depth in struct pci_dev. pci_ats_queue_depth() is typically called only once per device, and it returns a fixed value per-device, so callers who need the value frequently can cache it themselves. Signed-off-by: Bjorn Helgaas bhelg...@google.com --- drivers/pci

[PATCH v2 03/11] PCI: Embed ATS info directly into struct pci_dev

The pci_ats struct is small and will get smaller, so I don't think it's worth allocating it separately from the pci_dev struct. Embed the ATS fields directly into struct pci_dev. Signed-off-by: Bjorn Helgaas bhelg...@google.com --- drivers/pci/ats.c | 61

[PATCH v2 04/11] PCI: Reduce size of ATS structure elements

The extended capabilities list is linked with 12-bit pointers, and the ATS Smallest Translation Unit and Invalidate Queue Depth fields are both 5 bits. Use u16 and u8 to hold the extended capability address and the stu and qdep values. No functional change. Signed-off-by: Bjorn Helgaas bhelg

[PATCH v2 08/11] PCI: Clean up ATS error handling

these error paths. Signed-off-by: Bjorn Helgaas bhelg...@google.com --- drivers/pci/ats.c | 10 +- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/pci/ats.c b/drivers/pci/ats.c index 0b5b0ed..67524a7 100644 --- a/drivers/pci/ats.c +++ b/drivers/pci/ats.c @@ -44,11 +44,12

[PATCH v2 00/11] PCI: Fix ATS deadlock

associated VFs have ATS enabled - Add comment that ATS must be enabled on PF before on VFs - Require ATS to be disabled on all VFs and PF before changing STU --- Bjorn Helgaas (11): iommu/vt-d: Cache PCI ATS state and Invalidate Queue Depth PCI: Allocate ATS struct during enumeration

[PATCH v2 01/11] iommu/vt-d: Cache PCI ATS state and Invalidate Queue Depth

struct. This is similar to what amd_iommu.c does. Signed-off-by: Bjorn Helgaas bhelg...@google.com --- drivers/iommu/intel-iommu.c | 26 -- 1 file changed, 16 insertions(+), 10 deletions(-) diff --git a/drivers/iommu/intel-iommu.c b/drivers/iommu/intel-iommu.c index

[PATCH v2 09/11] PCI: Move ATS declarations to linux/pci.h so they're all together

Move ATS declarations to linux/pci.h so they're all in one place. Signed-off-by: Bjorn Helgaas bhelg...@google.com Reviewed-by: Joerg Roedel jroe...@suse.de --- include/linux/pci-ats.h | 41 - include/linux/pci.h | 10 +- 2 files changed, 9

[PATCH v2 05/11] PCI: Rationalize pci_ats_queue_depth() error checking

We previously returned -ENODEV for devices that don't support ATS (except that we always returned 0 for VFs, whether or not they support ATS). For consistency, always return -EINVAL (not -ENODEV) if the device doesn't support ATS. Return zero for VFs that support ATS. Signed-off-by: Bjorn

[PATCH v2 07/11] PCI: Use pci_physfn() rather than looking up physfn by hand

Use the pci_physfn() helper rather than looking up physfn by hand. No functional change. Signed-off-by: Bjorn Helgaas bhelg...@google.com Reviewed-by: Joerg Roedel jroe...@suse.de --- drivers/pci/ats.c |8 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/pci

[PATCH v2 06/11] PCI: Inline the ATS setup code into pci_ats_init()

The ATS setup code in ats_alloc_one() is only used by pci_ats_init(), so inline it there. No functional change. Signed-off-by: Bjorn Helgaas bhelg...@google.com Reviewed-by: Joerg Roedel jroe...@suse.de --- drivers/pci/ats.c |7 +-- 1 file changed, 1 insertion(+), 6 deletions(-) diff

<    1   2   3   4   5   >