On 1/7/21 1:09 PM, Florian Fainelli wrote:
On 1/7/21 9:57 AM, Konrad Rzeszutek Wilk wrote:
On Fri, Jan 08, 2021 at 01:39:18AM +0800, Claire Chang wrote:
Hi Greg and Konrad,
This change is intended to be non-arch specific. Any arch that lacks DMA access
control and has devices not behind an
Khalid,
Thanks for these patches. We will test them on x86 and investigate the Arm
pieces highlighted.
Jon.
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Computer Architect
> On Apr 4, 2019, at 00:37, Khalid Aziz wrote:
>
> This is another update to the work Juerg, Tycho and Julian have
> done on XPFO. After the last round of
On 05/09/2016 06:00 AM, Robin Murphy wrote:
> On 09/05/16 10:37, Robin Murphy wrote:
>> Hi Niklas,
>>
>> On 08/05/16 11:59, Niklas Söderlund wrote:
>>> Hi,
>>>
>>> While using CONFIG_DMA_API_DEBUG i came across this warning which I
>>> think is a false positive. As shown
On 05/05/2017 10:58 AM, Will Deacon wrote:
> On Fri, May 05, 2017 at 07:56:17AM -0700, David Daney wrote:
>> On 05/05/2017 06:53 AM, Hanjun Guo wrote:
>>> On 2017/5/5 20:08, Geetha sowjanya wrote:
From: Linu Cherian
+#define ACPI_IORT_SMMU_V3_CAVIUM_CN99XX
On 05/03/2017 05:47 AM, Will Deacon wrote:
> Hi Geetha,
>
> On Tue, May 02, 2017 at 12:01:15PM +0530, Geetha Akula wrote:
>> SMMU_IIDR register is broken on T99, that the reason we are using MIDR.
>
> Urgh, that's unfortunate. In what way is it broken?
>
>> If using MIDR is not accepted, can we
approaches to the case of cross-socket PCIe. But my
operating assumption is that anything longer term which looks boring and
x86 enough is probably fine from an ARM server point of view.
On 04/19/2017 07:38 PM, Jon Masters wrote:
> Hi Bjorn, JC,
>
> On 04/13/2017 08:19 PM, Bjorn Helg
Hi Bjorn, JC,
On 04/13/2017 08:19 PM, Bjorn Helgaas wrote:
> I tentatively applied both patches to pci/host-thunder for v4.12.
Thanks for that :)
> However, I am concerned about the topology here:
Various feedback has been provided on this one over the past $time. In
addition, I have
On 04/04/2017 10:28 AM, Robin Murphy wrote:
> So (at the risk of Jon mooing at me)
m
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On 04/11/2017 11:27 AM, Jayachandran C wrote:
> On Tue, Apr 11, 2017 at 08:41:25AM -0500, Bjorn Helgaas wrote:
>> I suspect the reason this patch makes a difference is because the
>> current pci_for_each_dma_alias() believes one of those top-level
>> bridges is an alias, and the iterator produces
On 03/22/2017 04:51 AM, Jayachandran C wrote:
> Hi Bjorn, Alex,
>
> Here is v3 of the patchset to handle the PCIe topology quirk of
> Cavium ThunderX2 (previously called Broadcom Vulcan).
>
> The earlier discussions on this can be seen at:
> http://www.spinics.net/lists/linux-pci/msg51001.html
>
On 11/07/2016 07:45 PM, Will Deacon wrote:
> I figured this was a reasonable post to piggy-back on for the LPC minutes
> relating to guest MSIs on arm64.
Thanks for this Will. I'm still digging out post-LPC and SC16, but the
summary was much appreciated, and I'm glad the conversation is helping.
and quirks in place.
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Computer Architect | Sent from my 64-bit #ARM Powered phone
> On Jun 23, 2016, at 08:04, Robin Murphy <robin.mur...@arm.com> wrote:
>
>> On 23/06/16 06:01, Jon Masters wrote:
>>> On 05/11/2016 10:26 AM, Robin Murphy wrote:
>>> (I have no ac
On 05/11/2016 10:26 AM, Robin Murphy wrote:
> (I have no actual objection to this patch, though, and at this point
> I'm just chucking ideas about).
Can I ask what the next steps are here? We're looking for upstream
direction to guide some internal activities and could really do with
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