> -Original Message-
> From: iommu On Behalf Of Koba Ko
> Sent: Sunday, June 14, 2020 10:47 PM
> To: David Woodhouse; Lu Baolu; Joerg Roedel
> Cc: iommu@lists.linux-foundation.org; Kai Heng Feng; Linux Kernel Mailing
> List
> Subject: [Issue]platform/x86: iommu: System can't shutdown becau
> -Original Message-
> From: iommu On Behalf Of Lu
> Baolu
> Sent: Monday, July 20, 2020 7:17 PM
> To: Joerg Roedel
> Cc: Ashok Raj; linux-ker...@vger.kernel.org; sta...@vger.kernel.org; Koba
> Ko; iommu@lists.linux-foundation.org
> Subject: [PATCH 1/1] iommu/vt-d: Skip TE disabling on qui
> -Original Message-
> From: Lu Baolu
> Sent: Tuesday, July 21, 2020 6:07 PM
> To: Limonciello, Mario; Joerg Roedel
> Cc: baolu...@linux.intel.com; Ashok Raj; linux-ker...@vger.kernel.org;
> sta...@vger.kernel.org; Koba Ko; iommu@lists.linux-foundation.org
> Su
[Public]
> On Tue, Mar 15, 2022 at 11:24:55AM -0500, Mario Limonciello wrote:
> > -* handled natively using IOMMU. It is enabled when IOMMU is
> > -* enabled and ACPI DMAR table has DMAR_PLATFORM_OPT_IN set.
> > +* handled natively using IOMMU. It is enabled when the IOMMU is
> > +
+ Christian Kellner (Bolt userspace maintainer)
On 3/15/2022 13:07, Robin Murphy wrote:
On 2022-03-15 16:54, Limonciello, Mario via iommu wrote:
[Public]
On Tue, Mar 15, 2022 at 11:24:55AM -0500, Mario Limonciello wrote:
- * handled natively using IOMMU. It is enabled when IOMMU is
[Public]
> -Original Message-
> From: Limonciello, Mario
> Sent: Tuesday, March 15, 2022 13:36
> To: Robin Murphy ; Christoph Hellwig
> ; christ...@kellner.me; Mika Westerberg
>
> Cc: Michael Jamet ; open list:THUNDERBOLT
> DRIVER ; open list ker...@vger.kern
rg; iommu@lists.linux-foundation.org; Limonciello,
> Mario ; h...@lst.de
> Subject: Re: [PATCH] thunderbolt: Stop using iommu_present()
>
> Hi Robin,
>
> On Wed, Mar 16, 2022 at 11:25:51AM +, Robin Murphy wrote:
> > Even if an IOMMU might be present for some PCI segment in the
[Public]
> On Wed, Mar 16, 2022 at 02:49:09PM +, Robin Murphy wrote:
> > > What we want is to make sure the Tunneled PCIe ports get the full
> IOMMU
> > > protection. In case of the discrete above it is also fine if all the
> > > devices behind the PCIe root port get the full IOMMU protection.
[Public]
> >>>
> >>> There is a way to figure out the "tunneled" PCIe ports by looking at
> >>> certain properties and we do that already actually. The BIOS has the
> >>> following under these ports:
> >>>
> >>>
> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fdocs
> >>> .micros
[Public]
> -Original Message-
> From: Limonciello, Mario
> Sent: Wednesday, March 16, 2022 12:54
> To: Robin Murphy ; Mika Westerberg
>
> Cc: michael.ja...@intel.com; linux-...@vger.kernel.org; linux-
> ker...@vger.kernel.org; yehezkel...@gmail.com; iommu@lists.li
[Public]
> > Can the USB4 CM make the device links in the DVSEC case perhaps too? I
> would
> > think we want that anyway to control device suspend ordering.
> >
> > If I had something discrete to try I'd dust off the DVSEC patch I wrote
> before to
> > try it, but alas all I have is integrated s
[Public]
> -Original Message-
> From: Robin Murphy
> Sent: Wednesday, March 16, 2022 14:18
> To: Limonciello, Mario ; Mika Westerberg
>
> Cc: michael.ja...@intel.com; linux-...@vger.kernel.org; linux-
> ker...@vger.kernel.org; yehezkel...@gmail.com; iommu@lists.li
gt; iommu@lists.linux-foundation.org; linux-...@vger.kernel.org; Limonciello,
> Mario
> Subject: [PATCH] thunderbolt: Make iommu_dma_protection more accurate
>
> Between me trying to get rid of iommu_present() and Mario wanting to
> support the AMD equivalent of DMAR_PLATFORM_OPT
[Public]
> -Original Message-
> From: Limonciello, Mario
> Sent: Thursday, March 17, 2022 12:09
> To: Robin Murphy ; andreas.noe...@gmail.com;
> michael.ja...@intel.com; mika.westerb...@linux.intel.com;
> yehezkel...@gmail.com
> Cc: linux-...@vger.
[Public]
> -Original Message-
> From: Robin Murphy
> Sent: Friday, March 18, 2022 09:08
> To: mika.westerb...@linux.intel.com
> Cc: Limonciello, Mario ;
> andreas.noe...@gmail.com; michael.ja...@intel.com;
> yehezkel...@gmail.com; linux-...@vger.ker
[Public]
> Between me trying to get rid of iommu_present() and Mario wanting to
> support the AMD equivalent of DMAR_PLATFORM_OPT_IN, scrutiny has
> shown
> that the iommu_dma_protection attribute is being far too optimistic.
> Even if an IOMMU might be present for some PCI segment in the system,
[Public]
> -Original Message-
> From: Robin Murphy
> Sent: Monday, March 21, 2022 06:12
> To: mika.westerb...@linux.intel.com; Limonciello, Mario
>
> Cc: j...@8bytes.org; baolu...@linux.intel.com; andreas.noe...@gmail.com;
> michael.ja...@intel.com; yehezke
[AMD Official Use Only]
> On Mon, Apr 04, 2022 at 11:47:05AM -0500, Mario Limonciello wrote:
> > The bounce buffers were originally set up, but torn down during
> > the boot process.
> > * This happens because as part of IOMMU initialization
> > `amd_iommu_init_dma_ops` gets called and resets th
[Public]
> -Original Message-
> From: Christoph Hellwig
> Sent: Monday, April 4, 2022 23:34
> To: Limonciello, Mario
> Cc: Joerg Roedel ; Will Deacon ;
> Christoph Hellwig ; Marek Szyprowski
> ; Robin Murphy ;
> open list:IOMMU DRIVERS ;
> Suthikulpan
[AMD Official Use Only]
> On Wed, Apr 06, 2022 at 05:04:52PM +0000, Limonciello, Mario wrote:
> > Considering before this fix effectively swiotlb was turned off on most AMD
> > systems, when this is picked up I think y'all should consider to add a:
> >
> > C
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