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On 11/06/2019 17:55, Lorenzo Pieralisi wrote:
> On Thu, Mar 28, 2019 at 05:59:48PM +0100, Marc Gonzalez wrote:
>
>> After a lot of poking, I am finally able to use the AR8151 ethernet on the
>> APQ8098 board.
>> The magic bit
On 05/06/2019 14:19, Will Deacon wrote:
> On Mon, Jun 03, 2019 at 02:15:37PM +0200, Marc Gonzalez wrote:
>
>> From: Robin Murphy
>>
>> Apparently, some Qualcomm arm64 platforms which appear to expose their
>> SMMU global register space are still, in fact, us
of the TLB maintenance where crashes
have been reported, so is apparently not a problem... :/
Reported-by: AngeloGioacchino Del Regno
Tested-by: Marc Gonzalez
Signed-off-by: Robin Murphy
Signed-off-by: Marc Gonzalez
---
Changes from v2:
- Define and use QCOM_DUMMY_VAL for the 3 problematic mmio writes
On 29/05/2019 15:05, Will Deacon wrote:
> On Wed, May 29, 2019 at 01:55:48PM +0200, Marc Gonzalez wrote:
>
>> From: Robin Murphy
>>
>> Apparently, some Qualcomm arm64 platforms which appear to expose their
>> SMMU global register space are still, in fact, us
of the TLB maintenance where crashes
have been reported, so is apparently not a problem... :/
Reported-by: AngeloGioacchino Del Regno
Reviewed-by: Marc Gonzalez
Reviewed-by: Bjorn Andersson
Tested-by: AngeloGioacchino Del Regno
Tested-by: Marc Gonzalez
Tested-by: Bjorn Andersson
Signed-off-by: Robin
+robh, +mrutland for DT
On 01/04/2019 17:44, Marc Gonzalez wrote:
> Unused at the moment, just future-proofing the DTS.
>
> Signed-off-by: Marc Gonzalez
> ---
> Documentation/devicetree/bindings/iommu/arm,smmu.txt | 1 +
> 1 file changed, 1 insertion(+)
>
> di
+robh, +mrutland for DT
On 01/04/2019 17:40, Marc Gonzalez wrote:
> The MSM8998 ANOC1(*) SMMU services BLSP2, PCIe, UFS, and USB.
> (*) Aggregate Network-on-Chip #1
>
> Based on the following DTS downstream:
> https://source.codeaurora.org/quic/la/kernel/msm-4.4/tree/arch/arm/bo
On 11/04/2019 11:09, Stanimir Varbanov wrote:
> On 4/11/19 11:44 AM, Marc Gonzalez wrote:
>
>> Since we just want to map 0x100, we don't need an iommu-map-mask.
>
> Do you see warnings during boot about missing property?
Absent iommu-map-mask property is expected.
On 10/04/2019 17:32, Stanimir Varbanov wrote:
> Few comments inline.
I'll send v3.
Changes:
- Move all X-names props *after* corresponding X(s) prop
- Drop comments
>> +iommu-map = <0x100 _smmu 0x1480 1>;
>
> iommu-map-mask? It is optional but I had to ask
On 28/03/2019 18:06, Marc Gonzalez wrote:
> Add MSM8998 PCIe QMP PHY and PCIe root complex DT nodes.
I suppose I should add a reference to the downstream DTS:
https://source.codeaurora.org/quic/la/kernel/msm-4.4/tree/arch/arm/boot/dts/qcom/msm8998.dtsi?h=LE.UM.1.3.r3.25#n2537
> diff
to pass through the SMMU.");
>
OK, so my defconfig contains neither IOMMU_DEFAULT_PASSTHROUGH nor
ARM_SMMU_DISABLE_BYPASS_BY_DEFAULT.
Thus my .config contains:
# CONFIG_IOMMU_DEFAULT_PASSTHROUGH is not set
CONFIG_ARM_SMMU_DISABLE_BYPASS_BY_DEFAULT=y
I have checked that disable_bypass is ind
On 02/04/2019 10:08, Stanimir Varbanov wrote:
> On 3/28/19 7:01 PM, Marc Gonzalez wrote:
>
>> Initialize PCIE20_PARF_BDF_TRANSLATE_N for ops_2_3_2.
>>
>> Signed-off-by: Marc Gonzalez
>> ---
>> drivers/pci/controller/dwc/pcie-qcom.c | 4
>> 1 file
On 01/04/2019 17:40, Marc Gonzalez wrote:
> The MSM8998 ANOC1(*) SMMU services BLSP2, PCIe, UFS, and USB.
> (*) Aggregate Network-on-Chip #1
>
> Based on the following DTS downstream:
> https://source.codeaurora.org/quic/la/kernel/msm-4.4/tree/arch/arm/boot/dts/qcom/msm-arm-s
Unused at the moment, just future-proofing the DTS.
Signed-off-by: Marc Gonzalez
---
Documentation/devicetree/bindings/iommu/arm,smmu.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.txt
b/Documentation/devicetree/bindings/iommu/arm
The MSM8998 ANOC1(*) SMMU services BLSP2, PCIe, UFS, and USB.
(*) Aggregate Network-on-Chip #1
Based on the following DTS downstream:
https://source.codeaurora.org/quic/la/kernel/msm-4.4/tree/arch/arm/boot/dts/qcom/msm-arm-smmu-8998.dtsi?h=LE.UM.1.3.r3.25#n18
Signed-off-by: Marc Gonzalez
On 28/03/2019 18:05, Marc Gonzalez wrote:
> ANOC1 SMMU filters PCIe accesses.
I'm not sure this description is entirely accurate...
ANOC likely stands for "Application Network-On-Chip"
> arch/arm64/boot/dts/qcom/msm8998.dtsi | 15 +++
> 1 file changed, 15 inse
Initialize PCIE20_PARF_BDF_TRANSLATE_N for ops_2_3_2.
Signed-off-by: Marc Gonzalez
---
drivers/pci/controller/dwc/pcie-qcom.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/pci/controller/dwc/pcie-qcom.c
b/drivers/pci/controller/dwc/pcie-qcom.c
index 0ed235d560e3..5e5522a427b8
Add MSM8998 PCIe QMP PHY and PCIe root complex DT nodes.
Signed-off-by: Marc Gonzalez
---
arch/arm64/boot/dts/qcom/msm8998.dtsi | 78 +++
1 file changed, 78 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/msm8998.dtsi
b/arch/arm64/boot/dts/qcom/msm8998.dtsi
index
ANOC1 SMMU filters PCIe accesses.
Signed-off-by: Marc Gonzalez
---
arch/arm64/boot/dts/qcom/msm8998.dtsi | 15 +++
1 file changed, 15 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/msm8998.dtsi
b/arch/arm64/boot/dts/qcom/msm8998.dtsi
index f9a922fdae75..5a1c0961b281 100644
Hello everyone,
After a lot of poking, I am finally able to use the AR8151 ethernet on the
APQ8098 board.
The magic bits are the iommu-map prop and the PCIE20_PARF_BDF_TRANSLATE_N setup.
The WIP thread is archived here:
https://marc.info/?t=15505953924=1=2
Marc Gonzalez (3):
PCI: qcom
On 21/03/2019 00:07, Robin Murphy wrote:
> Unfortunately, having looked around the code, I think I do. 4.4 long
> predates the iommu-map binding, and in the absence of anything other
> than the hard-coded SID==RID assumption of arm-smmu at the time, they
> apparently went and did their own
On 01/03/2019 20:20, Douglas Anderson wrote:
> If you're bisecting why your peripherals stopped working, it's
> probably this CL. Specifically if you see this in your dmesg:
> Unexpected global fault, this could be serious
> ...then it's almost certainly this CL.
>
> Running your
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