Hi Will,
>
> Is this workaround only needed for bypass STEs? If not, we have a problem
> when we install a stage-1 entry, because we'll clear the EATS bits as it
> stands.
>
Yes, this _was_ needed only in Bypass STEs, AFAIK.
However, the h/w fixes that were committed recently has this worked o
> Ok -- so what is the value reported by your IDR5?
Our IDR5, OAS=0x4 (44bits)
>
> Ok, I just didn't see any mention of that in the commit message and wanted
> to make sure it wasn't an accidental unrelated change.
>
Got it.
/Prem
___
iommu mailin
Hi Will, Thanks for the review.
> On Mon, Dec 14, 2015 at 10:01:27PM +0530, Prem Mallappa wrote:
> > Vulcan SMMUv3 looks for AARCH64 and S2PS inroder to validate the STE
> > entry,
>
> 'inroder' ?
>
In order
> > which is a overkill, but when proper encoding not found; the SMMU
> > stops processi
Hi Will,
It is ready, in internal review, will be sending it in a day.
/Prem
> -Original Message-
> From: Will Deacon [mailto:will.dea...@arm.com]
> Sent: 12 December 2015 01:23 AM
> To: Prem (Premachandra) Mallappa
> Cc: iommu@lists.linux-foundation.org
> -Original Message-
> From: Will Deacon [mailto:will.dea...@arm.com]
> Sent: 17 November 2015 11:17 PM
> To: Prem (Premachandra) Mallappa
> Cc: iommu@lists.linux-foundation.org; linux-arm-ker...@lists.infradead.org;
> Jayachandran Chandrashekaran Nair
> Subject: R
