On Thu, Jul 13, 2017 at 9:53 AM, Sricharan R wrote:
> Hi,
>
> On 7/13/2017 5:20 PM, Rob Clark wrote:
>> On Thu, Jul 13, 2017 at 1:35 AM, Sricharan R
>> wrote:
>>> Hi Vivek,
>>>
>>> On 7/13/2017 10:43 AM, Vivek Gautam wrote:
>>>> Hi
On Thu, Jul 13, 2017 at 8:02 AM, Marek Szyprowski
wrote:
> Hi All,
>
> On 2017-07-13 13:50, Rob Clark wrote:
>>
>> On Thu, Jul 13, 2017 at 1:35 AM, Sricharan R
>> wrote:
>>>
>>> On 7/13/2017 10:43 AM, Vivek Gautam wrote:
>>>>
>>>
Cc: devicet...@vger.kernel.org
Signed-off-by: Rob Clark
Reviewed-by: Rob Herring
---
.../devicetree/bindings/iommu/qcom,iommu.txt | 121 +
1 file changed, 121 insertions(+)
create mode 100644 Documentation/devicetree/bindings/iommu/qcom,iommu.txt
diff --git a
From: Stanimir Varbanov
This basically gets the secure page table size, allocates memory for
secure pagetables and passes the physical address to the trusted zone.
Signed-off-by: Stanimir Varbanov
Signed-off-by: Rob Clark
---
drivers/iommu/qcom_iommu.c | 64
e that all the dependencies for this driver have been merged
since 4.12, and it is the last thing needed for having another fully-
enabled (gpu/display/video codec/etc) ARM device that is fully upstream.
Rob Clark (3):
Docs: dt: document qcom iommu bindings
iommu: arm-smmu: split out regist
I want to re-use some of these for qcom_iommu, which has (roughly) the
same context-bank registers.
Signed-off-by: Rob Clark
---
drivers/iommu/arm-smmu-regs.h | 227 ++
drivers/iommu/arm-smmu.c | 203 +
2 files
devicetree instead of setting it up dynamically.
In the end, other than register definitions, there is not much code to
share with arm-smmu (other than what has already been refactored out
into the pgtable helpers).
Signed-off-by: Rob Clark
Tested-by: Riku Voipio
---
v1: original
v2: bindings cl
On Thu, Jul 13, 2017 at 5:50 AM, Robin Murphy wrote:
> On 13/07/17 07:48, Stephen Boyd wrote:
>> On 07/13, Vivek Gautam wrote:
>>> Hi Stephen,
>>>
>>>
>>> On 07/13/2017 04:24 AM, Stephen Boyd wrote:
On 07/06, Vivek Gautam wrote:
> @@ -1231,12 +1237,18 @@ static int arm_smmu_map(struct iom
On Thu, Jul 13, 2017 at 1:35 AM, Sricharan R wrote:
> Hi Vivek,
>
> On 7/13/2017 10:43 AM, Vivek Gautam wrote:
>> Hi Stephen,
>>
>>
>> On 07/13/2017 04:24 AM, Stephen Boyd wrote:
>>> On 07/06, Vivek Gautam wrote:
@@ -1231,12 +1237,18 @@ static int arm_smmu_map(struct iommu_domain
*domai
From: Stanimir Varbanov
This basically gets the secure page table size, allocates memory for
secure pagetables and passes the physical address to the trusted zone.
Signed-off-by: Stanimir Varbanov
Signed-off-by: Rob Clark
---
drivers/iommu/qcom_iommu.c | 64
devicetree instead of setting it up dynamically.
In the end, other than register definitions, there is not much code to
share with arm-smmu (other than what has already been refactored out
into the pgtable helpers).
Signed-off-by: Rob Clark
Tested-by: Riku Voipio
---
v1: original
v2: bindings cl
Cc: devicet...@vger.kernel.org
Signed-off-by: Rob Clark
Reviewed-by: Rob Herring
---
.../devicetree/bindings/iommu/qcom,iommu.txt | 121 +
1 file changed, 121 insertions(+)
create mode 100644 Documentation/devicetree/bindings/iommu/qcom,iommu.txt
diff --git a
I want to re-use some of these for qcom_iommu, which has (roughly) the
same context-bank registers.
Signed-off-by: Rob Clark
---
drivers/iommu/arm-smmu-regs.h | 227 ++
drivers/iommu/arm-smmu.c | 203 +
2 files
An iommu driver for Qualcomm "B" family devices which do not implement
the ARM SMMU spec in a way that is compatible with the arm-smmu driver.
Rob Clark (3):
Docs: dt: document qcom iommu bindings
iommu: arm-smmu: split out register defines
iommu: add qcom_iommu
Stanimir V
devicetree instead of setting it up dynamically.
In the end, other than register definitions, there is not much code to
share with arm-smmu (other than what has already been refactored out
into the pgtable helpers).
Signed-off-by: Rob Clark
Tested-by: Riku Voipio
---
v1: original
v2: bindings cl
From: Stanimir Varbanov
This basically gets the secure page table size, allocates memory for
secure pagetables and passes the physical address to the trusted zone.
Signed-off-by: Stanimir Varbanov
Signed-off-by: Rob Clark
---
drivers/iommu/qcom_iommu.c | 64
Cc: devicet...@vger.kernel.org
Signed-off-by: Rob Clark
Reviewed-by: Rob Herring
---
.../devicetree/bindings/iommu/qcom,iommu.txt | 121 +
1 file changed, 121 insertions(+)
create mode 100644 Documentation/devicetree/bindings/iommu/qcom,iommu.txt
diff --git a
An iommu driver for Qualcomm "B" family devices which do not implement
the ARM SMMU spec in a way that is compatible with the arm-smmu driver.
No change since last time, other than Riku's tested-by.
Rob Clark (3):
Docs: dt: document qcom iommu bindings
iommu: arm-smmu: spl
I want to re-use some of these for qcom_iommu, which has (roughly) the
same context-bank registers.
Signed-off-by: Rob Clark
---
drivers/iommu/arm-smmu-regs.h | 227 ++
drivers/iommu/arm-smmu.c | 203 +
2 files
devicetree instead of setting it up dynamically.
In the end, other than register definitions, there is not much code to
share with arm-smmu (other than what has already been refactored out
into the pgtable helpers).
Signed-off-by: Rob Clark
---
v1: original
v2: bindings cleanups and kconfig i
On Fri, May 26, 2017 at 8:56 AM, Robin Murphy wrote:
>> + struct iommu_group *group;
>
> This feels weird, since a device can be associated with multiple
> contexts, but only one group, so group-per-context is somewhat redundant
> and smacks of being in the wrong place. Does the firmware
I want to re-use some of these for qcom_iommu, which has (roughly) the
same context-bank registers.
Signed-off-by: Rob Clark
---
drivers/iommu/arm-smmu-regs.h | 227 ++
drivers/iommu/arm-smmu.c | 203 +
2 files
From: Stanimir Varbanov
This basically gets the secure page table size, allocates memory for
secure pagetables and passes the physical address to the trusted zone.
Signed-off-by: Stanimir Varbanov
Signed-off-by: Rob Clark
---
drivers/iommu/qcom_iommu.c | 64
devicetree instead of setting it up dynamically.
In the end, other than register definitions, there is not much code to
share with arm-smmu (other than what has already been refactored out
into the pgtable helpers).
Signed-off-by: Rob Clark
---
drivers/iommu/Kconfig | 10 +
drivers/iomm
Cc: devicet...@vger.kernel.org
Signed-off-by: Rob Clark
Reviewed-by: Rob Herring
---
.../devicetree/bindings/iommu/qcom,iommu.txt | 121 +
1 file changed, 121 insertions(+)
create mode 100644 Documentation/devicetree/bindings/iommu/qcom,iommu.txt
diff --git a
An iommu driver for Qualcomm "B" family devices which do not implement
the ARM SMMU spec in a way that is compatible with the arm-smmu driver.
Since last version, a few updates to 3/4 based on Robin's suggestions.
Rob Clark (3):
Docs: dt: document qcom iommu bindings
iommu:
On Fri, May 26, 2017 at 8:56 AM, Robin Murphy wrote:
> On 25/05/17 18:33, Rob Clark wrote:
>> An iommu driver for Qualcomm "B" family devices which do not completely
>> implement the ARM SMMU spec. These devices have context-bank register
>> layout that is sim
On Fri, May 26, 2017 at 7:33 AM, Robin Murphy wrote:
> On 25/05/17 18:33, Rob Clark wrote:
>> Cc: devicet...@vger.kernel.org
>> Signed-off-by: Rob Clark
>> Reviewed-by: Rob Herring
>> ---
>> .../devicetree/bindings/iommu/qcom,iommu.txt | 121
>> +
An iommu driver for Qualcomm "B" family devices which do not completely
implement the ARM SMMU spec. These devices have context-bank register
layout that is similar to ARM SMMU, but no global register space (or at
least not one that is accessible).
Signed-off-by: Rob Clark
---
v1: o
I want to re-use some of these for qcom_iommu, which has (roughly) the
same context-bank registers.
Signed-off-by: Rob Clark
---
drivers/iommu/arm-smmu-regs.h | 227 ++
drivers/iommu/arm-smmu.c | 203 +
2 files
From: Stanimir Varbanov
This basically gets the secure page table size, allocates memory for
secure pagetables and passes the physical address to the trusted zone.
Signed-off-by: Stanimir Varbanov
Signed-off-by: Rob Clark
---
drivers/iommu/qcom_iommu.c | 64
Cc: devicet...@vger.kernel.org
Signed-off-by: Rob Clark
Reviewed-by: Rob Herring
---
.../devicetree/bindings/iommu/qcom,iommu.txt | 121 +
1 file changed, 121 insertions(+)
create mode 100644 Documentation/devicetree/bindings/iommu/qcom,iommu.txt
diff --git a
/4, and dt bindings now have Rob H's r-b.
Rob Clark (3):
Docs: dt: document qcom iommu bindings
iommu: arm-smmu: split out register defines
iommu: add qcom_iommu
Stanimir Varbanov (1):
iommu: qcom: initialize secure page table
.../devicetree/bindings/iommu/qcom,iommu.txt | 121 +++
On Thu, May 11, 2017 at 11:08 AM, Sricharan R wrote:
> Hi Rob,
>
>
>
>> +static irqreturn_t qcom_iommu_fault(int irq, void *dev)
>> +{
>> + struct qcom_iommu_ctx *ctx = dev;
>> + u32 fsr, fsynr;
>> + unsigned long iova;
>> +
>> + fsr = iommu_readl(ctx, ARM_SMMU_CB_FSR);
>> +
>> +
An iommu driver for Qualcomm "B" family devices which do not completely
implement the ARM SMMU spec. These devices have context-bank register
layout that is similar to ARM SMMU, but no global register space (or at
least not one that is accessible).
Signed-off-by: Rob Clark
Sig
On Fri, May 5, 2017 at 3:50 PM, Rob Herring wrote:
> On Fri, May 5, 2017 at 2:37 PM, Rob Clark wrote:
>> On Fri, May 5, 2017 at 3:04 PM, Rob Herring wrote:
>>> On Fri, May 5, 2017 at 1:21 PM, Rob Clark wrote:
>>>> An iommu driver for Qualcomm "B"
On Fri, May 5, 2017 at 3:58 PM, Greg KH wrote:
> On Fri, May 05, 2017 at 02:56:00PM -0400, Rob Clark wrote:
>> On Fri, May 5, 2017 at 2:24 PM, Greg KH wrote:
>> > On Fri, May 05, 2017 at 02:08:37PM -0400, Rob Clark wrote:
>> >> It looks like it *used* to make sens
On Fri, May 5, 2017 at 3:04 PM, Rob Herring wrote:
> On Fri, May 5, 2017 at 1:21 PM, Rob Clark wrote:
>> An iommu driver for Qualcomm "B" family devices which do not completely
>> implement the ARM SMMU spec. These devices have context-bank register
>> layout that
On Fri, May 5, 2017 at 2:24 PM, Greg KH wrote:
> On Fri, May 05, 2017 at 02:08:37PM -0400, Rob Clark wrote:
>> It looks like it *used* to make sense to free the device. But now it is
>> embedded in 'struct iommu' (which is allocated or embedded in something
>
An iommu driver for Qualcomm "B" family devices which do not completely
implement the ARM SMMU spec. These devices have context-bank register
layout that is similar to ARM SMMU, but no global register space (or at
least not one that is accessible).
Signed-off-by: Rob Clark
---
v1: o
ings for struct iommu_device")
Signed-off-by: Rob Clark
---
drivers/iommu/iommu-sysfs.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/iommu/iommu-sysfs.c b/drivers/iommu/iommu-sysfs.c
index c58351e..ad19cbb 100644
--- a/drivers/iommu/iommu-sysfs.c
+++ b/drivers/iommu/iommu-sy
From: Stanimir Varbanov
This basically gets the secure page table size, allocates memory for
secure pagetables and passes the physical address to the trusted zone.
Signed-off-by: Stanimir Varbanov
Signed-off-by: Rob Clark
---
drivers/iommu/qcom_iommu.c | 64
Cc: devicet...@vger.kernel.org
Signed-off-by: Rob Clark
---
.../devicetree/bindings/iommu/qcom,iommu.txt | 121 +
1 file changed, 121 insertions(+)
create mode 100644 Documentation/devicetree/bindings/iommu/qcom,iommu.txt
diff --git a/Documentation/devicetree/bindings
I want to re-use some of these for qcom_iommu, which has (roughly) the
same context-bank registers.
Signed-off-by: Rob Clark
---
drivers/iommu/arm-smmu-regs.h | 227 ++
drivers/iommu/arm-smmu.c | 203 +
2 files
An iommu driver for Qualcomm "B" family devices which do not completely
implement the ARM SMMU spec. These devices have context-bank register
layout that is similar to ARM SMMU, but no global register space (or at
least not one that is accessible).
Signed-off-by: Rob Clark
Sig
eported by Archit
Rob Clark (3):
Docs: dt: document qcom iommu bindings
iommu: arm-smmu: split out register defines
iommu: add qcom_iommu
Stanimir Varbanov (1):
iommu: qcom: initialize secure page table
.../devicetree/bindings/iommu/qcom,iommu.txt | 121 +++
drivers/iom
On Fri, Mar 31, 2017 at 1:54 PM, Will Deacon wrote:
> On Thu, Mar 09, 2017 at 09:05:43PM +0530, Sricharan R wrote:
>> This series provides the support for turning on the arm-smmu's
>> clocks/power domains using runtime pm. This is done using the
>> recently introduced device links patches, which l
On Thu, Mar 30, 2017 at 2:19 AM, Archit Taneja wrote:
> Hi,
>
> On 03/14/2017 08:48 PM, Rob Clark wrote:
>>
>> An iommu driver for Qualcomm "B" family devices which do not completely
>> implement the ARM SMMU spec. These devices have context-bank register
On Thu, Mar 23, 2017 at 6:21 PM, Rob Herring wrote:
> On Tue, Mar 14, 2017 at 11:18:05AM -0400, Rob Clark wrote:
>> Cc: devicet...@vger.kernel.org
>> Signed-off-by: Rob Clark
>> ---
>> .../devicetree/bindings/iommu/qcom,iommu.txt | 113
>>
On Mon, Mar 20, 2017 at 10:21 AM, Sricharan R wrote:
> Hi Rob,
>
> sorry for the delayed response. Was not there mostly last week.
>
>
> On 3/13/2017 11:49 PM, Rob Clark wrote:
>>
>> On Mon, Mar 13, 2017 at 9:38 AM, wrote:
>>>
>>&g
On Thu, Mar 9, 2017 at 10:35 AM, Sricharan R wrote:
> The MMU400x/500 is the implementation of the SMMUv2
> arch specification. It is split in to two blocks
> TBU, TCU. TBU caches the page table, instantiated
> for each master locally, clocked by the TBUn_clk.
> TCU manages the address translation
Signed-off-by: Rob Clark
---
arch/arm64/boot/dts/qcom/msm8916.dtsi | 57 +++
1 file changed, 57 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi
b/arch/arm64/boot/dts/qcom/msm8916.dtsi
index 7bcf4cd..8aeec6f 100644
--- a/arch/arm64/boot/dts/qcom
From: Stanimir Varbanov
Signed-off-by: Stanimir Varbanov
Signed-off-by: Rob Clark
---
arch/arm64/boot/dts/qcom/msm8916.dtsi | 28
1 file changed, 28 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi
b/arch/arm64/boot/dts/qcom/msm8916.dtsi
index
Signed-off-by: Rob Clark
---
arch/arm64/boot/dts/qcom/msm8916.dtsi | 23 +++
1 file changed, 23 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi
b/arch/arm64/boot/dts/qcom/msm8916.dtsi
index 68a8e67..b0daf39 100644
--- a/arch/arm64/boot/dts/qcom/msm8916.dtsi
An iommu driver for Qualcomm "B" family devices which do not completely
implement the ARM SMMU spec. These devices have context-bank register
layout that is similar to ARM SMMU, but no global register space (or at
least not one that is accessible).
Signed-off-by: Rob Clark
Sig
From: Stanimir Varbanov
This basically gets the secure page table size, allocates memory for
secure pagetables and passes the physical address to the trusted zone.
Signed-off-by: Stanimir Varbanov
Signed-off-by: Rob Clark
---
drivers/iommu/qcom_iommu.c | 64
I want to re-use some of these for qcom_iommu, which has (roughly) the
same context-bank registers.
Signed-off-by: Rob Clark
---
drivers/iommu/arm-smmu-regs.h | 225 ++
drivers/iommu/arm-smmu.c | 200 +
2 files
From: Stanimir Varbanov
Those two new SCM calls are needed from qcom-iommu driver in order
to initialize secure iommu page table.
Signed-off-by: Stanimir Varbanov
Signed-off-by: Rob Clark
---
drivers/firmware/qcom_scm-32.c | 12
drivers/firmware/qcom_scm-64.c | 42
b410c-qcom-smmu-3-venus
or github if you prefer:
https://github.com/freedreno/kernel-msm/commits/next-20170307-db410c-qcom-smmu-3-venus
Compared to previous patchset, there have been some (mostly binding related)
cleanups. Also fixed some other-config related build issues that kbuild
robot spo
Signed-off-by: Rob Clark
---
drivers/firmware/qcom_scm-32.c | 6 ++
drivers/firmware/qcom_scm-64.c | 16
drivers/firmware/qcom_scm.c| 6 ++
drivers/firmware/qcom_scm.h| 5 +
include/linux/qcom_scm.h | 2 ++
5 files changed, 35 insertions(+)
diff
Cc: devicet...@vger.kernel.org
Signed-off-by: Rob Clark
---
.../devicetree/bindings/iommu/qcom,iommu.txt | 113 +
1 file changed, 113 insertions(+)
create mode 100644 Documentation/devicetree/bindings/iommu/qcom,iommu.txt
diff --git a/Documentation/devicetree/bindings
On Mon, Mar 13, 2017 at 9:38 AM, wrote:
> Hi Rob,
>
> [..]
>
>
>> +static int qcom_iommu_init_domain(struct iommu_domain *domain,
>> + struct qcom_iommu_dev *qcom_iommu,
>> + struct iommu_fwspec *fwspec)
>> +{
>> + struct qcom_
On Tue, Mar 7, 2017 at 12:48 PM, Robin Murphy wrote:
> On 01/03/17 17:42, Rob Clark wrote:
>> An iommu driver for Qualcomm "B" family devices which do not completely
>> implement the ARM SMMU spec.
>
> Is that actually true, or is it just that it's a compli
On Fri, Mar 3, 2017 at 1:21 AM, Rob Herring wrote:
> On Wed, Mar 01, 2017 at 12:42:52PM -0500, Rob Clark wrote:
>
> Nit: use "dt-bindings: iommu: ..." for subject. And a commit message
> would be nice.
>
>> Cc: devicet...@vger.kernel.org
>> Signed-off-by:
On Wed, Mar 1, 2017 at 6:54 PM, Stephen Boyd wrote:
> On 03/01/2017 09:42 AM, Rob Clark wrote:
>> diff --git a/drivers/iommu/qcom_iommu.c b/drivers/iommu/qcom_iommu.c
>> new file mode 100644
>> index 000..5d3bb63
>> --- /dev/null
>> +++ b/drivers/iom
Signed-off-by: Rob Clark
---
arch/arm64/boot/dts/qcom/msm8916.dtsi | 57 +++
1 file changed, 57 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi
b/arch/arm64/boot/dts/qcom/msm8916.dtsi
index 7bcf4cd..10ca05a 100644
--- a/arch/arm64/boot/dts/qcom
Signed-off-by: Rob Clark
---
arch/arm64/boot/dts/qcom/msm8916.dtsi | 23 +++
1 file changed, 23 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi
b/arch/arm64/boot/dts/qcom/msm8916.dtsi
index 68a8e67..b0daf39 100644
--- a/arch/arm64/boot/dts/qcom/msm8916.dtsi
From: Stanimir Varbanov
Signed-off-by: Stanimir Varbanov
Signed-off-by: Rob Clark
---
arch/arm64/boot/dts/qcom/msm8916.dtsi | 28
1 file changed, 28 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi
b/arch/arm64/boot/dts/qcom/msm8916.dtsi
index
An iommu driver for Qualcomm "B" family devices which do not completely
implement the ARM SMMU spec. These devices have context-bank register
layout that is similar to ARM SMMU, but no global register space (or at
least not one that is accessible).
Signed-off-by: Rob Clark
---
dri
Signed-off-by: Rob Clark
---
drivers/firmware/qcom_scm-32.c | 6 ++
drivers/firmware/qcom_scm-64.c | 16
drivers/firmware/qcom_scm.c| 6 ++
drivers/firmware/qcom_scm.h| 5 +
include/linux/qcom_scm.h | 2 ++
5 files changed, 35 insertions(+)
diff
From: Stanimir Varbanov
This bassicaly get the secure page table size, allocate memory
and return back the physical address to the trusted zone.
Signed-off-by: Stanimir Varbanov
Signed-off-by: Rob Clark
---
drivers/iommu/qcom_iommu.c | 64 ++
1
I want to re-use some of these for qcom_iommu, which has (roughly) the
same context-bank registers.
Signed-off-by: Rob Clark
---
drivers/iommu/arm-smmu-regs.h | 225 ++
drivers/iommu/arm-smmu.c | 200 +
2 files
Cc: devicet...@vger.kernel.org
Signed-off-by: Rob Clark
---
.../devicetree/bindings/iommu/qcom,iommu.txt | 106 +
1 file changed, 106 insertions(+)
create mode 100644 Documentation/devicetree/bindings/iommu/qcom,iommu.txt
diff --git a/Documentation/devicetree/bindings
From: Stanimir Varbanov
Those two new SCM calls are needed from qcom-iommu driver in order
to initialize secure iommu page table.
Signed-off-by: Stanimir Varbanov
Signed-off-by: Rob Clark
---
drivers/firmware/qcom_scm-64.c | 42 ++
drivers/firmware
apply on top of some in-flight patches to support IOMMU
probe deferral. You can find full branch on top of linux-next here:
git://people.freedesktop.org/~robclark/linux
next-20170228-db410c-qcom-smmu-3-venus
or github if you prefer:
https://github.com/freedreno/kernel-msm/commits/ne
On Wed, Feb 22, 2017 at 4:31 AM, Sricharan wrote:
> Hi Rob,
>
>>diff --git a/Documentation/devicetree/bindings/iommu/qcom,iommu.txt
>>b/Documentation/devicetree/bindings/iommu/qcom,iommu.txt
>>new file mode 100644
>>index 000..78a8d65
>>--- /dev/null
>>+++ b/Documentation/devicetree/bindings/i
An iommu driver for Qualcomm "B" family devices which do not completely
implement the ARM SMMU spec. These devices have context-bank register
layout that is similar to ARM SMMU, but no global register space (or at
least not one that is accessible).
Signed-off-by: Rob Clark
---
Fe
I want to re-use some of these for qcom_iommu, which has (roughly) the
same context-bank registers.
Signed-off-by: Rob Clark
---
drivers/iommu/arm-smmu-regs.h | 225 ++
drivers/iommu/arm-smmu.c | 200 +
2 files
On Tue, Feb 14, 2017 at 1:46 PM, Robin Murphy wrote:
> Hi Rob,
>
> On 10/02/17 18:41, Rob Clark wrote:
>> For devices with iommu(s) in secure mode, we cannot touch global
>> registers, and we have to live with the context -> sid mapping that
>> the secure world
Signed-off-by: Rob Clark
---
drivers/firmware/qcom_scm-32.c | 6 ++
drivers/firmware/qcom_scm-64.c | 16
drivers/firmware/qcom_scm.c| 6 ++
drivers/firmware/qcom_scm.h| 5 +
include/linux/qcom_scm.h | 2 ++
5 files changed, 35 insertions(+)
diff
ways, at this point, I'm mostly just looking for feedback about
whether this is the best way forward, vs introducing a seperate iommu
driver, and any suggestions anyone might have. And any ideas about how
to best handle the secure context banks, since I think we have no
choice but to use
On Thu, Feb 2, 2017 at 10:12 AM, Will Deacon wrote:
> On Thu, Feb 02, 2017 at 10:02:50AM -0500, Rob Clark wrote:
>> On Thu, Jan 26, 2017 at 12:18 PM, Joerg Roedel wrote:
>> > On Tue, Jan 24, 2017 at 08:42:23PM +0530, Sricharan wrote:
>> >> Thanks for this seri
On Wed, Feb 1, 2017 at 11:10 PM, Sricharan wrote:
> Hi Rob,
>
>>On Wed, Feb 1, 2017 at 10:23 AM, Rob Clark wrote:
>>> Before the driver is probed, arm_smmu_add_device() helpfully attaches
>>> an IOMMU_DOMAIN_DMA domain. Which ofc does not support stalling, and
>
On Thu, Jan 26, 2017 at 12:18 PM, Joerg Roedel wrote:
> On Tue, Jan 24, 2017 at 08:42:23PM +0530, Sricharan wrote:
>> Thanks for this series. We had a case with the GPU.
>> The GPU's iommu was setup by kernel and the GPU
>> also does dynamic updates for on-the-fly switching between
>> process page
On Wed, Feb 1, 2017 at 11:10 PM, Sricharan wrote:
> Hi Rob,
>
>>On Wed, Feb 1, 2017 at 10:23 AM, Rob Clark wrote:
>>> Before the driver is probed, arm_smmu_add_device() helpfully attaches
>>> an IOMMU_DOMAIN_DMA domain. Which ofc does not support stalling, and
>
A new flag when registering the fault handler indicates that the user
supports stalling, and will call iommu_domain_resume() at some point
later, potentially from a workqueue. (This would allow the user to do
mm related operations that could not be done from irq context.)
Signed-off-by: Rob
On Wed, Feb 1, 2017 at 10:23 AM, Rob Clark wrote:
> Before the driver is probed, arm_smmu_add_device() helpfully attaches
> an IOMMU_DOMAIN_DMA domain. Which ofc does not support stalling, and
> when the driver later attaches a domain that can_stall to an smmu that
> can stall, the
TODO maybe some dev_dbg() or some other way to tell if stalling is
actually enabled?
Signed-off-by: Rob Clark
---
.../devicetree/bindings/iommu/arm,smmu.txt | 3 +
drivers/iommu/arm-smmu.c | 85 --
2 files changed, 82 insertions(+), 6
.html
Rob Clark (3):
iommu: introduce stall/resume support
iommu/arm-smmu: Add support to opt-in to stalling
iommu/arm-smmu: detach DMA domain if driver is managing iommu
.../devicetree/bindings/iommu/arm,smmu.txt | 3 +
drivers/gpu/drm/etnaviv/etnaviv_mmu.c
cause further problems later)
One simple way to deal with this is simply toss the default _DMA domain
if the driver attaches it's own domain.
TODO maybe the tracking of list of attached domains should be done in
iommu core, so the detach can happen outside of group->mutex.
Signed-off-by: R
On Thu, Jan 12, 2017 at 10:17 AM, Will Deacon wrote:
> On Wed, Jan 11, 2017 at 03:59:30PM -0500, Rob Clark wrote:
>> On Wed, Jan 11, 2017 at 4:36 AM, Will Deacon wrote:
>> > On Tue, Jan 10, 2017 at 02:20:13PM -0500, Rob Clark wrote:
>> >> On Tue, Jan 10, 2017 a
On Wed, Jan 11, 2017 at 4:36 AM, Will Deacon wrote:
> On Tue, Jan 10, 2017 at 02:20:13PM -0500, Rob Clark wrote:
>> On Tue, Jan 10, 2017 at 12:52 PM, Will Deacon wrote:
>> > On Fri, Jan 06, 2017 at 11:26:49AM -0500, Rob Clark wrote:
>> >> Hmm, well we in
On Tue, Jan 10, 2017 at 12:52 PM, Will Deacon wrote:
> Hi Rob,
>
> On Fri, Jan 06, 2017 at 11:26:49AM -0500, Rob Clark wrote:
>> On Thu, Jan 5, 2017 at 10:49 AM, Will Deacon wrote:
>> > On Thu, Jan 05, 2017 at 10:27:27AM -0500, Rob Clark wrote:
>> >> I&#x
On Thu, Jan 5, 2017 at 12:25 PM, Will Deacon wrote:
>> That's still got to be a per-master property, not a SMMU property, I
>> think. To illustrate:
>>
>> [A] [B] [C]
>>| |_|
>> __|__|___
>> | TBU || TBU |
>> |_| SMMU |_|
>> |__|
On Thu, Jan 5, 2017 at 10:49 AM, Will Deacon wrote:
> On Thu, Jan 05, 2017 at 10:27:27AM -0500, Rob Clark wrote:
>> On Thu, Jan 5, 2017 at 6:55 AM, Will Deacon wrote:
>> > On Tue, Jan 03, 2017 at 04:30:54PM -0500, Rob Clark wrote:
>> >> TODO maybe we want two option
On Thu, Jan 5, 2017 at 6:55 AM, Will Deacon wrote:
> On Tue, Jan 03, 2017 at 04:30:54PM -0500, Rob Clark wrote:
>> TODO maybe we want two options, one to enable stalling, and 2nd to punt
>> handling to wq? I haven't needed to use mm APIs from fault handler yet
>> (altho
On Wed, Jan 4, 2017 at 9:31 AM, Rob Clark wrote:
> On Wed, Jan 4, 2017 at 8:33 AM, Sricharan wrote:
>> Hi,
>>
>>>-Original Message-
>>>From: linux-arm-msm-ow...@vger.kernel.org
>>>[mailto:linux-arm-msm-ow...@vger.kernel.org] On Behalf Of Jo
On Wed, Jan 4, 2017 at 8:33 AM, Sricharan wrote:
> Hi,
>
>>-Original Message-
>>From: linux-arm-msm-ow...@vger.kernel.org
>>[mailto:linux-arm-msm-ow...@vger.kernel.org] On Behalf Of Jordan Crouse
>>Sent: Wednesday, January 04, 2017 3:59 AM
>>To:
At least on the db820c I have, with the firmware I have, I'm not seeing
the SS bit set, even though the iommu is in a stalled state. So for
this implementation ignore not having SS bit set.
Signed-off-by: Rob Clark
---
drivers/iommu/arm-smmu.c | 6 ++
1 file changed, 6 insertions(+)
Let the iommu user ask the iommu to terminate the transaction without
printing any error msg via -EFAULT return.
(Alternatively, look for -ENOSYS return instead to trigger the msg?)
Signed-off-by: Rob Clark
---
drivers/iommu/arm-smmu.c | 12 ++--
1 file changed, 10 insertions(+), 2
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