The IOMMUv2 APIs (for supporting shared virtual memory with PASID)
configures the domain with IOMMU v2 page table, and sets DTE[Mode]=0.
This configuration cannot be supported on SNP-enabled system.
Signed-off-by: Suravee Suthikulpanit
---
drivers/iommu/amd/init.c | 7 ++-
1 file changed, 6
.
* Remove function stub when CONFIG_AMD_MEM_ENCRYPT is not set.
- Patch 6: Change to WARN_ONCE.
Best Regards,
Suravee
Brijesh Singh (1):
iommu/amd: Introduce function to check and enable SNP
Suravee Suthikulpanit (6):
iommu/amd: Warn when found inconsistency EFR mask
iommu/amd
-by: Robin Murphy
Signed-off-by: Suravee Suthikulpanit
---
drivers/iommu/amd/iommu.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/iommu/amd/iommu.c b/drivers/iommu/amd/iommu.c
index 4f4571d3ff61..7093e26fec59 100644
--- a/drivers/iommu/amd/iommu.c
+++ b/drivers/iommu/amd/iommu.c
and determines
if the feature can be safely enabled.
Please see the IOMMU spec section 2.12 for further details.
Reviewed-by: Robin Murphy
Co-developed-by: Suravee Suthikulpanit
Signed-off-by: Suravee Suthikulpanit
Signed-off-by: Brijesh Singh
---
drivers/iommu/amd/amd_iommu_types.h | 5
-by: Suravee Suthikulpanit
---
drivers/iommu/amd/init.c | 3 ++-
drivers/iommu/amd/iommu.c | 15 +--
2 files changed, 15 insertions(+), 3 deletions(-)
diff --git a/drivers/iommu/amd/init.c b/drivers/iommu/amd/init.c
index c62fb4470519..f5695ccb7c81 100644
--- a/drivers/iommu/amd
is
initialized before enabling the rest of IOMMU features.
Also report IOMMU SNP support information for each IOMMU.
Signed-off-by: Suravee Suthikulpanit
---
drivers/iommu/amd/init.c | 12
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/drivers/iommu/amd/init.c b
through all
IOMMUs even when found that the bit is not set, and also throws a FW_BUG
warning if inconsistency is found.
Signed-off-by: Suravee Suthikulpanit
---
drivers/iommu/amd/init.c | 19 +++
1 file changed, 15 insertions(+), 4 deletions(-)
diff --git a/drivers/iommu/amd
of the IVRS table for all IOMMU instances.
This allow all IVHDs to be processed prior to enabling features.
Phase2 : Early feature support check on all IOMMUs (using information in
IVHD blocks.
Phase3 : Iterates through all IOMMU instances and enabling features.
Signed-off-by: Suravee
and determines
if the feature can be safely enabled.
Please see the IOMMU spec section 2.12 for further details.
Co-developed-by: Suravee Suthikulpanit
Signed-off-by: Suravee Suthikulpanit
Signed-off-by: Brijesh Singh
---
drivers/iommu/amd/amd_iommu_types.h | 5
drivers/iommu/amd/init.c
of the IVRS table for all IOMMU instances.
This allow all IVHDs to be processed prior to enabling features.
Phase2 : Early feature support check on all IOMMUs (using information in
IVHD blocks.
Phase3 : Iterates through all IOMMU instances and enabling features.
Signed-off-by: Suravee
The IOMMUv2 APIs (for supporting shared virtual memory with PASID)
configures the domain with IOMMU v2 page table, and sets DTE[Mode]=0.
This configuration cannot be supported on SNP-enabled system.
Signed-off-by: Suravee Suthikulpanit
---
drivers/iommu/amd/init.c | 7 ++-
1 file changed, 6
-by: Suravee Suthikulpanit
---
drivers/iommu/amd/iommu.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/drivers/iommu/amd/iommu.c b/drivers/iommu/amd/iommu.c
index 4f4571d3ff61..d8a6df423b90 100644
--- a/drivers/iommu/amd/iommu.c
+++ b/drivers/iommu/amd/iommu.c
@@ -2119,6 +2119,15
is
initialized before enabling the rest of IOMMU features.
Also report IOMMU SNP support information for each IOMMU.
Signed-off-by: Suravee Suthikulpanit
---
drivers/iommu/amd/init.c | 12
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/drivers/iommu/amd/init.c b
-by: Suravee Suthikulpanit
---
drivers/iommu/amd/init.c | 3 ++-
drivers/iommu/amd/iommu.c | 15 +--
2 files changed, 15 insertions(+), 3 deletions(-)
diff --git a/drivers/iommu/amd/init.c b/drivers/iommu/amd/init.c
index b5d3de327a5f..bc008a82c12c 100644
--- a/drivers/iommu/amd
declaration to include/linux/amd-iommu.h
- Patch 6: Modify amd_iommu_domain_alloc() to fail when allocating identity
domain and SNP is enabled.
Best Regards,
Suravee
Brijesh Singh (1):
iommu/amd: Introduce function to check and enable SNP
Suravee Suthikulpanit (6):
iommu/amd: Warn when
through all
IOMMUs even when found that the bit is not set, and also throws a FW_BUG
warning if inconsistency is found.
Signed-off-by: Suravee Suthikulpanit
---
drivers/iommu/amd/init.c | 19 +++
1 file changed, 15 insertions(+), 4 deletions(-)
diff --git a/drivers/iommu/amd
Since DTE[Mode]=0 is prohibited on system, which enables SNP,
the passthrough domain (IOMMU_DOMAIN_IDENTITY) is not support.
Instead, only support IOMMU_DOMAIN_DMA[_FQ] domains.
Signed-off-by: Suravee Suthikulpanit
---
drivers/iommu/amd/iommu.c | 12
1 file changed, 12 insertions
Suthikulpanit
Signed-off-by: Suravee Suthikulpanit
Signed-off-by: Brijesh Singh
---
drivers/iommu/amd/amd_iommu_types.h | 11
drivers/iommu/amd/init.c| 39 ++---
drivers/iommu/amd/iommu.c | 4 +--
include/linux/iommu.h | 9
-by: Suravee Suthikulpanit
---
drivers/iommu/amd/init.c | 3 ++-
drivers/iommu/amd/iommu.c | 15 +--
2 files changed, 15 insertions(+), 3 deletions(-)
diff --git a/drivers/iommu/amd/init.c b/drivers/iommu/amd/init.c
index da32e7bdd1fa..a9152d3f33bf 100644
--- a/drivers/iommu/amd
The IOMMUv2 APIs (for supporting shared virtual memory with PASID)
configures the domain with IOMMU v2 page table, and sets DTE[Mode]=0.
This configuration cannot be supported on SNP-enabled system.
Signed-off-by: Suravee Suthikulpanit
---
drivers/iommu/amd/init.c | 7 ++-
1 file changed, 6
of the IVRS table for all IOMMU instances.
This allow all IVHDs to be processed prior to enabling features.
Phase 2 iterates through all IOMMU instances and enabling each features.
Signed-off-by: Suravee Suthikulpanit
---
drivers/iommu/amd/init.c | 20 ++--
1 file changed, 14
-by: Suravee Suthikulpanit
---
drivers/iommu/amd/init.c | 42 ++--
1 file changed, 40 insertions(+), 2 deletions(-)
diff --git a/drivers/iommu/amd/init.c b/drivers/iommu/amd/init.c
index 6a4a019f1e1d..3965bd3f4f67 100644
--- a/drivers/iommu/amd/init.c
+++ b/drivers
not match the default type.
Introducing check_domain_type_supported() callback in iommu_ops,
which allows IOMMU generic layer to check with vendor-specific IOMMU driver
whether the requested type is supported. This allows user to request
types other than the default type.
Signed-off-by: Suravee
/amd: Introduce function to check SEV-SNP support
Suravee Suthikulpanit (6):
iommu/amd: Process all IVHDs before enabling IOMMU features
iommu/amd: Introduce a global variable for tracking SNP enable status
iommu/amd: Set translation valid bit only when IO page tables are in
use
iommu
On 4/29/22 4:09 AM, Joao Martins wrote:
AMD implementation of unmap_read_dirty() is pretty simple as
mostly reuses unmap code with the extra addition of marshalling
the dirty bit into the bitmap as it walks the to-be-unmapped
IOPTE.
Extra care is taken though, to switch over to cmpxchg as
Joao,
On 4/29/22 4:09 AM, Joao Martins wrote:
.
+static int amd_iommu_set_dirty_tracking(struct iommu_domain *domain,
+ bool enable)
+{
+ struct protection_domain *pdomain = to_pdomain(domain);
+ struct iommu_dev_data *dev_data;
+ bool
Joerg,
On 5/20/22 3:09 PM, Joerg Roedel wrote:
Hi Suravee,
On Mon, May 16, 2022 at 07:27:51PM +0700, Suravee Suthikulpanit wrote:
- Also, it seems that the current iommu v2 page table use case, where
GVA->GPA=SPA
will no longer be supported on system w/ SNPSup=1. Any thoughts?
Supp
Joerg,
On 5/13/22 8:07 PM, Joerg Roedel wrote:
On Mon, May 09, 2022 at 02:48:15AM -0500, Suravee Suthikulpanit wrote:
On AMD system with SNP enabled, IOMMU hardware checks the host translation
valid (TV) and guest translation valid (GV) bits in the device
table entry (DTE) before accessing
page table is in used.
This results in ILLEGAL_DEV_TABLE_ENTRY event for devices, which
do not the host page table root pointer set up.
Thefore, only set TV bit when DMA remapping is not used, which is
when domain ID in the AMD IOMMU device table entry (DTE) is zero.
Signed-off-by: Suravee
On 4/20/22 6:29 PM, Suravee Suthikulpanit wrote:
On AMD system with SNP enabled, IOMMU hardware checks the host translation
valid (TV) and guest translation valid (GV) bits in the device
table entry (DTE) before accessing the corresponded page tables.
However, current IOMMU driver sets
page table is in used.
This results in ILLEGAL_DEV_TABLE_ENTRY event for devices, which
do not the host page table root pointer set up.
Thefore, only set TV bit when host or guest page tables are in used.
Signed-off-by: Suravee Suthikulpanit
---
drivers/iommu/amd/init.c | 4 +---
drivers/iommu
: dc6a709e5123 ("iommu/amd: Improve amd_iommu_v2_exit()")
Signed-off-by: Suravee Suthikulpanit
---
drivers/iommu/amd/iommu_v2.c | 12 +++-
1 file changed, 11 insertions(+), 1 deletion(-)
diff --git a/drivers/iommu/amd/iommu_v2.c b/drivers/iommu/amd/iommu_v2.c
index 490da41c3c71..5a
updating the mode.
Cc: Joerg Roedel
Reported-by: Daniel Jordan
Tested-by: Daniel Jordan
Signed-off-by: Suravee Suthikulpanit
Fixes: e42ba0633064 ("iommu/amd: Restructure code for freeing page table")
Link: https://lore.kernel.org/all/20220118194720.urjgi73b7c3tq...@oracle.com/
---
drivers
Since the function has been simplified and only call iommu_init_ga_log(),
remove the function and replace with iommu_init_ga_log() instead.
Signed-off-by: Suravee Suthikulpanit
---
drivers/iommu/amd/init.c | 17 -
1 file changed, 4 insertions(+), 13 deletions(-)
diff --git
IOMMU advertises feature via Extended Features Register (EFR).
The helper function checks if the specified feature bit is set
across all IOMMUs.
Signed-off-by: Suravee Suthikulpanit
---
drivers/iommu/amd/init.c | 13 +
1 file changed, 13 insertions(+)
diff --git a/drivers/iommu/amd
entry_SYSCALL_64_after_hwframe+0x44/0xae
Fixes by moving the initializing of AMD IOMMU interrupt remapping mode
(amd_iommu_guest_ir) earlier before setting up the
amd_iommu_irq_ops.capability with appropriate IRQ_POSTING_CAP flag.
Signed-off-by: Wei Huang
Signed-off-by: Suravee Suthikulpanit
---
drivers/iommu/amd
,
which is available after PCI support for IOMMU is initialized.
This helps avoid having to disable and clean up the already
initialized interrupt-remapping-related parameter.
Thanks,
Suravee
Suravee Suthikulpanit (2):
iommu/amd: Introduce helper function to check feature bit on all
IOMMUs
To help review changes related to AMD IOMMU.
Signed-off-by: Suravee Suthikulpanit
---
MAINTAINERS | 1 +
1 file changed, 1 insertion(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index b80e6f7..8022dbd 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -933,6 +933,7 @@ F: drivers/video/fbdev/geode
Suggested-by: Alexander Monakov
Cc: David Coe
Signed-off-by: Suravee Suthikulpanit
---
arch/x86/events/amd/iommu.c | 47 -
1 file changed, 26 insertions(+), 21 deletions(-)
diff --git a/arch/x86/events/amd/iommu.c b/arch/x86/events/amd/iommu.c
index 1c
://lore.kernel.org/linux-iommu/alpine.lnx.3.20.13.2006030935570.3...@monopod.intra.ispras.ru/
Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=201753
Cc: Tj (Elloe Linux)
Cc: Shuah Khan
Cc: Alexander Monakov
Cc: David Coe
Signed-off-by: Paul Menzel
Signed-off-by: Suravee Suthikulpanit
---
Note
kernel.org/show_bug.cgi?id=201753
Cc: Tj (Elloe Linux)
Cc: Shuah Khan
Cc: Alexander Monakov
Cc: David Coe
Cc: Paul Menzel
Signed-off-by: Suravee Suthikulpanit
---
drivers/iommu/amd/init.c | 24 +---
1 file changed, 1 insertion(+), 23 deletions(-)
diff --git a/drivers/iommu/am
for helping to test, investigate, provide data
and report issues on several platforms in the field.
Regards,
Suravee
Paul Menzel (1):
Revert "iommu/amd: Fix performance counter initialization"
Suravee Suthikulpanit (1):
iommu/amd: Remove performance counter pre-initialization test
drivers
Joerg,
On 3/18/21 10:31 PM, Joerg Roedel wrote:
On Fri, Mar 12, 2021 at 03:04:09AM -0600, Suravee Suthikulpanit wrote:
@@ -519,6 +521,7 @@ struct protection_domain {
spinlock_t lock;/* mostly used to lock the page table*/
u16 id; /* the domain id written
Joerg,
On 3/18/21 10:33 PM, Joerg Roedel wrote:
On Fri, Mar 12, 2021 at 03:04:10AM -0600, Suravee Suthikulpanit wrote:
To allow specification whether to use v1 or v2 IOMMU pagetable for
DMA remapping when calling kernel DMA-API.
Signed-off-by: Suravee Suthikulpanit
---
Documentation/admin
Introduce init function for setting up DMA domain for DMA-API with
the IOMMU v2 page table.
Signed-off-by: Suravee Suthikulpanit
---
drivers/iommu/amd/iommu.c | 21 +
1 file changed, 21 insertions(+)
diff --git a/drivers/iommu/amd/iommu.c b/drivers/iommu/amd/iommu.c
index
To allow specification whether to use v1 or v2 IOMMU pagetable for
DMA remapping when calling kernel DMA-API.
Signed-off-by: Suravee Suthikulpanit
---
Documentation/admin-guide/kernel-parameters.txt | 6 ++
drivers/iommu/amd/init.c| 15 +++
2 files
-off-by: Suravee Suthikulpanit
---
drivers/iommu/amd/init.c | 19 +--
1 file changed, 5 insertions(+), 14 deletions(-)
diff --git a/drivers/iommu/amd/init.c b/drivers/iommu/amd/init.c
index 9126efcbaf2c..5def566de6f6 100644
--- a/drivers/iommu/amd/init.c
+++ b/drivers/iommu/amd
Introduce IO page table framework support for AMD IOMMU v2 page table.
Signed-off-by: Suravee Suthikulpanit
---
drivers/iommu/amd/Makefile | 2 +-
drivers/iommu/amd/amd_iommu_types.h | 2 +
drivers/iommu/amd/io_pgtable_v2.c | 239
drivers/iommu/io
The current function to enable IOMMU v2 also lock the domain.
In order to reuse the same code in different code path, in which
the domain has already been locked, refactor the function to separate
the locking from the enabling logic.
Signed-off-by: Suravee Suthikulpanit
---
drivers/iommu/amd
AMD IOMMU introduces support for Guest I/O protection where the request
from the I/O device without a PASID are treated as if they have PASID 0.
Signed-off-by: Suravee Suthikulpanit
---
drivers/iommu/amd/amd_iommu_types.h | 3 +++
drivers/iommu/amd/init.c| 8
drivers/iommu
Currently, PPR/ATS can be enabled only if the domain is type
identity mapping. However, when we allow the IOMMU v2 page table
to be used for DMA-API, the sanity check needs to be updated to
only apply for the case when using AMD_IOMMU_V1 page table mode.
Signed-off-by: Suravee Suthikulpanit
.
http://www.amd.com/system/files/TechDocs/48882_IOMMU_3.05_PUB.pdf
Thanks,
Suravee
Suravee Suthikulpanit (7):
iommu/amd: Refactor amd_iommu_domain_enable_v2
iommu/amd: Update sanity check when enable PRI/ATS
iommu/amd: Decouple the logic to enable PPR and GT
iommu/amd: Initial support
Paul,
On 3/3/21 7:11 PM, Paul Menzel wrote:
This reverts commit 6778ff5b21bd8e78c8bd547fd66437cf2657fd9b.
The commit adds up to 100 ms to the boot process, which is not mentioned
in the commit message, and is making up more than 20 % on current
systems, where the Linux kernel takes 500 ms.
:
On Tue, 16 Jun 2020, Suravee Suthikulpanit wrote:
Instead of blindly moving the code around to a spot that would just work,
I am trying to understand what might be required here. In this case,
the init_device_table_dma()should not be needed. I suspect it's the IOMMU
invalidate all command that's also
bug.cgi?id=201753
Signed-off-by: Suravee Suthikulpanit
---
drivers/iommu/amd/init.c | 45 ++--
1 file changed, 34 insertions(+), 11 deletions(-)
diff --git a/drivers/iommu/amd/init.c b/drivers/iommu/amd/init.c
index 83d8ab2aed9f..01da76dc1caa 100644
--- a/drivers
TJ,
Thanks for testing. I will submit this change upstream w/ you as Tested-by.
On 2/8/21 12:18 AM, Tj (Elloe Linux) wrote:
On 06/02/2021 04:02, Suravee Suthikulpanit wrote:
Would this be in any way related to the following from the same device:
kernel: pci :00:00.2: can't derive routing
to see if this works better on your platform.
Thanks,
Suravee
On 2/4/21 1:25 PM, Tj (Elloe Linux) wrote:
On 02/02/2021 05:54, Suravee Suthikulpanit wrote:
Could you please try the attached patch to see if the problem still
persist.
Tested on top of commit 61556703b610 doesn't appear to have solved
ed=0
From c103d631285cf376420e7f7869837302f2ac38c0 Mon Sep 17 00:00:00 2001
From: Suravee Suthikulpanit
Date: Mon, 1 Feb 2021 18:38:26 -0600
Subject: [RFC PATCH] iommu/amd: Fix performance counter initialization
Certain AMD platforms enable power gating feature for IOMMU PMC,
which prevents the IOMMU driver fro
On 1/27/21 7:06 PM, Joerg Roedel wrote:
Hi Suravee,
On Tue, Dec 15, 2020 at 01:36:52AM -0600, Suravee Suthikulpanit wrote:
Suravee Suthikulpanit (13):
iommu/amd: Re-define amd_iommu_domain_encode_pgtable as inline
iommu/amd: Prepare for generic IO page table framework
iommu/amd
available in the IVHD header, and is available to
the driver prior to PCI initialization. Therefore, default to using
the IVHD EFR instead.
Fixes: 6d39bdee238f ("iommu/amd: Enforce 4k mapping for certain IOMMU data
structures")
Reviewed-by: Robert Richter
Tested-by: Brijesh Singh
Si
I will send out v2 of this patch. Please ignore this v1.
Thanks,
Suravee
On 1/18/21 12:19 PM, Suravee Suthikulpanit wrote:
IOMMU Extended Feature Register (EFR) is used to communicate
the supported features for each IOMMU to the IOMMU driver.
This is normally read from the PCI MMIO register
instead.
Fixes: 6d39bdee238f ("iommu/amd: Enforce 4k mapping for certain IOMMU data
structures")
Tested-by: Brijesh Singh
Signed-off-by: Suravee Suthikulpanit
---
drivers/iommu/amd/amd_iommu.h | 3 ++-
drivers/iommu/amd/amd_iommu_types.h | 4 +++
drivers/iommu/amd/init.c
Hi Joerg / Will,
Happy New Year!! Just want to follow up on this series.
Thanks,
Suravee
On 12/15/20 2:36 PM, Suravee Suthikulpanit wrote:
The framework allows callable implementation of IO page table.
This allows AMD IOMMU driver to switch between different types
of AMD IOMMU page tables
To simplify the fetch_pte function. There is no functional change.
Signed-off-by: Suravee Suthikulpanit
---
drivers/iommu/amd/amd_iommu.h | 2 +-
drivers/iommu/amd/io_pgtable.c | 13 +++--
drivers/iommu/amd/iommu.c | 4 +++-
3 files changed, 11 insertions(+), 8 deletions
These implement map and unmap for AMD IOMMU v1 pagetable, which
will be used by the IO pagetable framework.
Also clean up unused extern function declarations.
Signed-off-by: Suravee Suthikulpanit
---
drivers/iommu/amd/amd_iommu.h | 13 -
drivers/iommu/amd/io_pgtable.c | 25
There is no functional change.
Signed-off-by: Suravee Suthikulpanit
---
drivers/iommu/amd/io_pgtable.c | 31 +++
1 file changed, 15 insertions(+), 16 deletions(-)
diff --git a/drivers/iommu/amd/io_pgtable.c b/drivers/iommu/amd/io_pgtable.c
index d4d131e43dcd
Since the IO page table root and mode parameters have been moved into
the struct amd_io_pg, the function is no longer needed. Therefore,
remove it along with the struct domain_pgtable.
Signed-off-by: Suravee Suthikulpanit
---
drivers/iommu/amd/amd_iommu.h | 4 ++--
drivers/iommu/amd
Switch to using IO page table framework for AMD IOMMU v1 page table.
Signed-off-by: Suravee Suthikulpanit
---
drivers/iommu/amd/amd_iommu.h | 1 +
drivers/iommu/amd/init.c | 2 ++
drivers/iommu/amd/iommu.c | 48 ++-
3 files changed, 39 insertions
Move the function to header file to allow inclusion in other files.
Signed-off-by: Suravee Suthikulpanit
---
drivers/iommu/amd/amd_iommu.h | 13 +
drivers/iommu/amd/iommu.c | 10 --
2 files changed, 13 insertions(+), 10 deletions(-)
diff --git a/drivers/iommu/amd
This implements iova_to_phys for AMD IOMMU v1 pagetable,
which will be used by the IO page table framework.
Signed-off-by: Suravee Suthikulpanit
---
drivers/iommu/amd/io_pgtable.c | 22 ++
drivers/iommu/amd/iommu.c | 16 +---
2 files changed, 23 insertions
Preparing to migrate to use IO page table framework.
There is no functional change.
Signed-off-by: Suravee Suthikulpanit
---
drivers/iommu/amd/amd_iommu.h | 18 ++
drivers/iommu/amd/io_pgtable.c | 473
drivers/iommu/amd/iommu.c | 476
And move declaration to header file so that they can be included across
multiple files. There is no functional change.
Signed-off-by: Suravee Suthikulpanit
---
drivers/iommu/amd/amd_iommu.h | 3 +++
drivers/iommu/amd/iommu.c | 39 +--
2 files changed, 22
By consolidate logic into v1_free_pgtable helper function,
which is called from IO page table framework.
Signed-off-by: Suravee Suthikulpanit
---
drivers/iommu/amd/amd_iommu.h | 1 -
drivers/iommu/amd/io_pgtable.c | 41 --
drivers/iommu/amd/iommu.c | 21
Make use of the new struct amd_io_pgtable in preparation to remove
the struct domain_pgtable.
Signed-off-by: Suravee Suthikulpanit
---
drivers/iommu/amd/amd_iommu.h | 1 +
drivers/iommu/amd/iommu.c | 25 ++---
2 files changed, 11 insertions(+), 15 deletions(-)
diff
To better organize the data structure since it contains IO page table
related information.
Signed-off-by: Suravee Suthikulpanit
---
drivers/iommu/amd/amd_iommu.h | 2 +-
drivers/iommu/amd/amd_iommu_types.h | 2 +-
drivers/iommu/amd/iommu.c | 2 +-
3 files changed, 3 insertions
Add initial hook up code to implement generic IO page table framework.
Signed-off-by: Suravee Suthikulpanit
---
drivers/iommu/amd/Kconfig | 1 +
drivers/iommu/amd/Makefile | 2 +-
drivers/iommu/amd/amd_iommu_types.h | 35 ++
drivers/iommu/amd/io_pgtable.c
/23/251)
- Do not specify struct io_pgtable_cfg.coherent_walk, since it is
not currently used. (per Robin)
- Remove unused struct iommu_flush_ops. (patch 2/13)
- Move amd_iommu_setup_io_pgtable_ops to iommu.c instead of io_pgtable.c
patch 13/13)
Suravee Suthikulpanit (13):
iommu/amd:
of the DTE[IntTabLen] field as
specified in the AMD IOMMU specification. There is no functional change.
Suggested-by: Linus Torvalds
Reviewed-by: Tom Lendacky
Signed-off-by: Suravee Suthikulpanit
Cc: Will Deacon
Cc: Jerry Snitselaar
Cc: Joerg Roedel
---
drivers/iommu/amd/amd_iommu_types.h | 19
u/amd: Increase interrupt remapping table limit to
512 entries")
Reported-by: Jerry Snitselaar
Signed-off-by: Suravee Suthikulpanit
---
drivers/iommu/amd/amd_iommu_types.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/iommu/amd/amd_iommu_types.h
b/drivers/iommu/a
Will,
To answer your questions from v1 thread.
On 11/18/20 5:57 AM, Will Deacon wrote:
> On 11/5/20 9:58 PM, Suravee Suthikulpanit wrote:
>> AMD IOMMU requires 4k-aligned pages for the event log, the PPR log,
>> and the completion wait write-back regions. However, when allocati
Will,
I have already submitted v2 of this patch. Let me move the discussion there
instead ...
(https://lore.kernel.org/linux-iommu/20201105145832.3065-1-suravee.suthikulpa...@amd.com/)
Suravee
On 11/18/20 5:57 AM, Will Deacon wrote:
On Wed, Oct 28, 2020 at 11:18:24PM +, Suravee
Joerg,
Please ignore to include the V3. I am working on V4 to resubmit.
Thank you,
Suravee
On 11/11/20 10:10 AM, Suravee Suthikulpanit wrote:
Hi Joerg,
Do you have any update on this series?
Thanks,
Suravee
On 11/2/20 10:16 AM, Suravee Suthikulpanit wrote:
Joerg,
You mentioned to remind
Hi Joerg,
Do you have any update on this series?
Thanks,
Suravee
On 11/2/20 10:16 AM, Suravee Suthikulpanit wrote:
Joerg,
You mentioned to remind you to pull this in to linux-next.
Thanks,
Suravee
On 10/4/20 8:45 AM, Suravee Suthikulpanit wrote:
The framework allows callable
for these data structures.
So, fix by calling set_memory_4k() on the allocated pages.
Fixes: commit c69d89aff393 ("iommu/amd: Use 4K page for completion wait
write-back semaphore")
Cc: Brijesh Singh
Signed-off-by: Suravee Suthikulpanit
---
drivers/iommu/amd/init.c | 27 ++---
Joerg,
You mentioned to remind you to pull this in to linux-next.
Thanks,
Suravee
On 10/4/20 8:45 AM, Suravee Suthikulpanit wrote:
The framework allows callable implementation of IO page table.
This allows AMD IOMMU driver to switch between different types
of AMD IOMMU page tables (e.g. v1 vs
for these data structures.
So, fix by calling set_memory_4k() on the allocated pages.
Fixes: commit c69d89aff393 ("iommu/amd: Use 4K page for completion wait
write-back semaphore")
Cc: Brijesh Singh
Signed-off-by: Suravee Suthikulpanit
---
drivers/iommu/amd/init.c | 22 +---
Hi Joerg,
Do you have any concerns regarding this patch?
Thanks,
Suravee
On 10/15/20 9:50 AM, Suravee Suthikulpanit wrote:
Certain device drivers allocate IO queues on a per-cpu basis.
On AMD EPYC platform, which can support up-to 256 cpu threads,
this can exceed the current MAX_IRQ_PER_TABLE
-by: Suravee Suthikulpanit
---
drivers/iommu/amd/amd_iommu_types.h | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/iommu/amd/amd_iommu_types.h
b/drivers/iommu/amd/amd_iommu_types.h
index 30a5d412255a..427484c45589 100644
--- a/drivers/iommu/amd/amd_iommu_types.h
+++ b
Introduce amd_iommu_free_pgtable helper function, which consolidates
logic for freeing page table.
Signed-off-by: Suravee Suthikulpanit
---
drivers/iommu/amd/amd_iommu.h | 2 +-
drivers/iommu/amd/io_pgtable.c | 12 +++-
drivers/iommu/amd/iommu.c | 19 ++-
3 files
This implements iova_to_phys for AMD IOMMU v1 pagetable,
which will be used by the IO page table framework.
Signed-off-by: Suravee Suthikulpanit
---
drivers/iommu/amd/io_pgtable.c | 22 ++
drivers/iommu/amd/iommu.c | 16 +---
2 files changed, 23 insertions
These implement map and unmap for AMD IOMMU v1 pagetable, which
will be used by the IO pagetable framework.
Also clean up unused extern function declarations.
Signed-off-by: Suravee Suthikulpanit
---
drivers/iommu/amd/amd_iommu.h | 13 -
drivers/iommu/amd/io_pgtable.c | 25
Switch to using IO page table framework for AMD IOMMU v1 page table.
Signed-off-by: Suravee Suthikulpanit
---
drivers/iommu/amd/iommu.c | 26 ++
1 file changed, 26 insertions(+)
diff --git a/drivers/iommu/amd/iommu.c b/drivers/iommu/amd/iommu.c
index 77f44b927ae7
Add TLB flush callback functions, which are used by the IO
page table framework.
Signed-off-by: Suravee Suthikulpanit
---
drivers/iommu/amd/io_pgtable.c | 29 +
1 file changed, 29 insertions(+)
diff --git a/drivers/iommu/amd/io_pgtable.c b/drivers/iommu/amd
struct iommu_flush_ops. (patch 2/13)
- Move amd_iommu_setup_io_pgtable_ops to iommu.c instead of io_pgtable.c
patch 13/13)
Suravee Suthikulpanit (14):
iommu/amd: Re-define amd_iommu_domain_encode_pgtable as inline
iommu/amd: Prepare for generic IO page table framework
iommu/amd: Move
There is no functional change.
Signed-off-by: Suravee Suthikulpanit
---
drivers/iommu/amd/io_pgtable.c | 31 +++
1 file changed, 15 insertions(+), 16 deletions(-)
diff --git a/drivers/iommu/amd/io_pgtable.c b/drivers/iommu/amd/io_pgtable.c
index 6c063d2c8bf0
Since the IO page table root and mode parameters have been moved into
the struct amd_io_pg, the function is no longer needed. Therefore,
remove it along with the struct domain_pgtable.
Signed-off-by: Suravee Suthikulpanit
---
drivers/iommu/amd/amd_iommu.h | 4 ++--
drivers/iommu/amd
Add initial hook up code to implement generic IO page table framework.
Signed-off-by: Suravee Suthikulpanit
---
drivers/iommu/amd/Kconfig | 1 +
drivers/iommu/amd/Makefile | 2 +-
drivers/iommu/amd/amd_iommu_types.h | 35 +++
drivers/iommu/amd
Make use of the new struct amd_io_pgtable in preparation to remove
the struct domain_pgtable.
Signed-off-by: Suravee Suthikulpanit
---
drivers/iommu/amd/amd_iommu.h | 1 +
drivers/iommu/amd/iommu.c | 25 ++---
2 files changed, 11 insertions(+), 15 deletions(-)
diff
Move the function to header file to allow inclusion in other files.
Signed-off-by: Suravee Suthikulpanit
---
drivers/iommu/amd/amd_iommu.h | 13 +
drivers/iommu/amd/iommu.c | 10 --
2 files changed, 13 insertions(+), 10 deletions(-)
diff --git a/drivers/iommu/amd
To better organize the data structure since it contains IO page table
related information.
Signed-off-by: Suravee Suthikulpanit
---
drivers/iommu/amd/amd_iommu.h | 2 +-
drivers/iommu/amd/amd_iommu_types.h | 2 +-
drivers/iommu/amd/iommu.c | 2 +-
3 files changed, 3 insertions
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