a caution.
Fixes: 83a3545d9c37 ("arm64: dts: marvell: add SMMU support")
Cc: # 5.9+
Signed-off-by: Tomasz Nowicki
---
arch/arm64/boot/dts/marvell/armada-7040.dtsi | 4
arch/arm64/boot/dts/marvell/armada-8040.dtsi | 4
2 files changed, 8 deletions(-)
diff --git a/arch/arm64/boot
On 10/23/20 12:33 PM, Robin Murphy wrote:
On 2020-10-23 13:19, Tomasz Nowicki wrote:
Hi Denis,
Sorry for late response, we had to check few things. Please see
comments inline.
On 10/6/20 3:16 PM, Denis Odintsov wrote:
Hi,
Am 15.07.2020 um 09:06 schrieb Tomasz Nowicki :
The series is
Hi Denis,
Sorry for late response, we had to check few things. Please see comments
inline.
On 10/6/20 3:16 PM, Denis Odintsov wrote:
Hi,
Am 15.07.2020 um 09:06 schrieb Tomasz Nowicki :
The series is meant to support SMMU for AP806 and a workaround
for accessing ARM SMMU 64bit registers is
On 15.07.2020 12:36, Robin Murphy wrote:
On 2020-07-15 08:06, Tomasz Nowicki wrote:
Add specific compatible string for Marvell usage due to errata of
accessing 64bits registers of ARM SMMU, in AP806.
AP806 SoC uses the generic ARM-MMU500, and there's no specific
implementation of Marvell,
On 15.07.2020 12:32, Robin Murphy wrote:
On 2020-07-15 08:06, Tomasz Nowicki wrote:
From: Hanna Hawa
Due to erratum #582743, the Marvell Armada-AP806 can't access 64bit to
ARM SMMUv2 registers.
Provide implementation relevant hooks:
- split the writeq/readq to two accesses of writel/
From: Marcin Wojtas
Add IOMMU node for Marvell AP806 based SoCs together with platform
and PCI device Stream ID mapping.
Signed-off-by: Marcin Wojtas
Signed-off-by: Tomasz Nowicki
---
arch/arm64/boot/dts/marvell/armada-7040.dtsi | 28 +
arch/arm64/boot/dts/marvell/armada-8040
Hanna Hawa
Signed-off-by: Gregory CLEMENT
Signed-off-by: Tomasz Nowicki
---
Documentation/devicetree/bindings/iommu/arm,smmu.yaml | 4
1 file changed, 4 insertions(+)
diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml
b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml
cted features before we start consuming them.
Since the Cavium quirk (the only user) does not alter features
it is safe to do so.
Suggested-by: Robin Murphy
Signed-off-by: Tomasz Nowicki
---
drivers/iommu/arm-smmu.c | 11 +++
1 file changed, 7 insertions(+), 4 deletions(-)
diff --git
ff-by: Gregory CLEMENT
Signed-off-by: Tomasz Nowicki
---
Documentation/arm64/silicon-errata.rst | 3 ++
drivers/iommu/arm-smmu-impl.c | 45 ++
2 files changed, 48 insertions(+)
diff --git a/Documentation/arm64/silicon-errata.rst
b/Documentation/arm64/si
s
Hanna Hawa (1):
iommu/arm-smmu: Workaround for Marvell Armada-AP806 SoC erratum
#582743
Marcin Wojtas (1):
arm64: dts: marvell: add SMMU support
Tomasz Nowicki (2):
iommu/arm-smmu: Call configuration impl hook before consuming features
dt-bindings: arm-smmu: add compatible string for
Hi Will,
On 14.07.2020 10:19, Will Deacon wrote:
Hi Tomasz,
On Thu, Jul 02, 2020 at 10:16:29PM +0200, Tomasz Nowicki wrote:
There were already two versions of series to support SMMU for AP806,
including workaround for accessing ARM SMMU 64bit registers.
First [1] by Hanna Hawa and second [2
On 03.07.2020 11:03, Robin Murphy wrote:
On 2020-07-02 21:16, Tomasz Nowicki wrote:
From: Hanna Hawa
Due to erratum #582743, the Marvell Armada-AP806 can't access 64bit to
ARM SMMUv2 registers.
Provide implementation relevant hooks:
- split the writeq/readq to two accesses of writel/
On 03.07.2020 11:16, Robin Murphy wrote:
On 2020-07-02 21:16, Tomasz Nowicki wrote:
From: Marcin Wojtas
Add IOMMU node for Marvell AP806 based SoCs together with platform
and PCI device Stream ID mapping.
Signed-off-by: Marcin Wojtas
Signed-off-by: Tomasz Nowicki
---
arch/arm64/boot/dts
On 03.07.2020 11:05, Robin Murphy wrote:
On 2020-07-02 21:16, Tomasz Nowicki wrote:
Add specific compatible string for Marvell usage due to errata of
accessing 64bits registers of ARM SMMU, in AP806.
AP806 SoC uses the generic ARM-MMU500, and there's no specific
implementation of Marvell,
On 03.07.2020 10:24, Robin Murphy wrote:
On 2020-07-02 21:16, Tomasz Nowicki wrote:
We already have 'cfg_probe' hook which meant to override and apply
workarounds while probing ID registers. However, 'cfg_probe' is called
at the very end and therefore for some cases fixi
ems it is better and
cleaner to do ID fixup right away. In preparation for adding Marvell
errata add an extra ID2 fixup hook.
Signed-off-by: Tomasz Nowicki
---
drivers/iommu/arm-smmu.c | 3 +++
drivers/iommu/arm-smmu.h | 1 +
2 files changed, 4 insertions(+)
diff --git a/drivers/iommu/arm-smmu.c
From: Marcin Wojtas
Add IOMMU node for Marvell AP806 based SoCs together with platform
and PCI device Stream ID mapping.
Signed-off-by: Marcin Wojtas
Signed-off-by: Tomasz Nowicki
---
arch/arm64/boot/dts/marvell/armada-8040.dtsi | 36 +++
arch/arm64/boot/dts/marvell/armada
e for platform devices like SATA and USB.
[1]: https://lkml.org/lkml/2018/10/15/373
[2]: https://lkml.org/lkml/2019/7/11/426
Hanna Hawa (1):
iommu/arm-smmu: Workaround for Marvell Armada-AP806 SoC erratum
#582743
Marcin Wojtas (1):
arm64: dts: marvell: add SMMU support
Tomasz Nowic
egory CLEMENT
Signed-off-by: Tomasz Nowicki
---
Documentation/devicetree/bindings/iommu/arm,smmu.yaml | 5 +
1 file changed, 5 insertions(+)
diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml
b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml
index d7ceb4c34423..7beca9c
d-off-by: Gregory CLEMENT
Signed-off-by: Tomasz Nowicki
---
Documentation/arm64/silicon-errata.rst | 3 ++
drivers/iommu/arm-smmu-impl.c | 52 ++
2 files changed, 55 insertions(+)
diff --git a/Documentation/arm64/silicon-errata.rst
b/Documentation/arm64/si
ertions(+), 3 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/virtio/iommu.txt
> create mode 100644 drivers/iommu/virtio-iommu.c
> create mode 100644 include/uapi/linux/virtio_iommu.h
>
I have tested the whole series and Eric&
Hi Jean,
On 14.02.2018 15:53, Jean-Philippe Brucker wrote:
The virtio IOMMU is a para-virtualized device, allowing to send IOMMU
requests such as map/unmap over virtio-mmio transport without emulating
page tables. This implementation handles ATTACH, DETACH, MAP and UNMAP
requests.
The bulk of t
Hi Robin,
On 19.12.2017 17:34, Robin Murphy wrote:
Hi Tomasz,
On 19/12/17 15:13, Tomasz Nowicki wrote:
Here is my lspci output of ThunderX2 for which I am observing kernel
panic coming from
SMMUv3 driver -> arm_smmu_write_strtab_ent() -> BUG_ON(ste_live):
# lspci -vt
-[:00]-+-00
On 19.12.2017 17:37, Alex Williamson wrote:
On Tue, 19 Dec 2017 16:20:21 +0100
Tomasz Nowicki wrote:
While iterating over DMA aliases for a PCI device, for some rare cases
(i.e. PCIe-to-PCI/X bridges) we may get exactly the same ID as initial child
device. In turn, the same ID may get
Hi Robin,
On 19.12.2017 17:34, Robin Murphy wrote:
Hi Tomasz,
On 19/12/17 15:13, Tomasz Nowicki wrote:
Here is my lspci output of ThunderX2 for which I am observing kernel
panic coming from
SMMUv3 driver -> arm_smmu_write_strtab_ent() -> BUG_ON(ste_live):
# lspci -vt
-[:00]-+-00
multiple times too which for some IOMMU drivers is illegal and causes kernel
panic.
Rule out ID duplication prior to device ID array registration.
CC: sta...@vger.kernel.org # v4.14+
Signed-off-by: Tomasz Nowicki
---
drivers/iommu/iommu.c | 28
1 file changed, 28
ossible to have two identical SIDs. The question is what we
should do about such case. Presented patch prevents from registering the same
ID so that SMMUv3 is not complaining later on.
Tomasz Nowicki (1):
iommu: Make sure device's ID array elements are unique
driver
Hi Joerg,
On 12.10.2017 12:04, Joerg Roedel wrote:
Hi Tomasz,
On Thu, Oct 12, 2017 at 11:40:27AM +0200, Tomasz Nowicki wrote:
Can you please have a look and see if you are fine with this patch?
How do these changes relate to Robin's IOVA optimizations already in the
iommu-tree?
Th
Hi Joerg,
Can you please have a look and see if you are fine with this patch?
Thanks in advance,
Tomasz
On 20.09.2017 10:52, Tomasz Nowicki wrote:
Here is my test setup where I have stareted performance measurements.
PCIe - TX - PCIe
Hi Joerg,
Can you please have a look and see if you are fine with this patch?
Thanks in advance,
Tomasz
On 20.09.2017 10:52, Tomasz Nowicki wrote:
Here is my test setup where I have stareted performance measurements.
PCIe - TX - PCIe
Hi Robin,
On 21.09.2017 17:52, Robin Murphy wrote:
The cached node mechanism provides a significant performance benefit for
allocations using a 32-bit DMA mask, but in the case of non-PCI devices
or where the 32-bit space is full, the loss of this benefit can be
significant - on large systems th
Hi Robin,
On 19.09.2017 18:31, Robin Murphy wrote:
The cached node mechanism provides a significant performance benefit for
allocations using a 32-bit DMA mask, but in the case of non-PCI devices
or where the 32-bit space is full, the loss of this benefit can be
significant - on large systems th
solution is that machines with relatively
small numbers of CPUs may get DAC addresses more frequently for PCI
devices. Please let me know your thoughts.
Changelog:
v1 --> v2
- add missing documentation
- fix typo
Tomasz Nowicki (1):
iommu/iova: Make rcache flush optional on IOVA allocatio
e we pick the slowest option
to proceed.
This patch reworks flushed_rcache local flag to be additional function
argument instead and control rcache flush step. Also, it updates all users
to do the flush as the last chance.
Signed-off-by: Tomasz Nowicki
Reviewed-by: Robin Murphy
Tested-by:
Hi Nate,
On 19.09.2017 04:57, Nate Watterson wrote:
Hi Tomasz,
On 9/18/2017 12:02 PM, Robin Murphy wrote:
Hi Tomasz,
On 18/09/17 11:56, Tomasz Nowicki wrote:
Since IOVA allocation failure is not unusual case we need to flush
CPUs' rcache in hope we will succeed in next round.
Howeve
Hi Robin,
On 18.09.2017 18:02, Robin Murphy wrote:
Hi Tomasz,
On 18/09/17 11:56, Tomasz Nowicki wrote:
Since IOVA allocation failure is not unusual case we need to flush
CPUs' rcache in hope we will succeed in next round.
However, it is useful to decide whether we need rcache flush
e we pick the slowest option
to proceed.
This patch reworks flushed_rcache local flag to be additional function
argument instead and control rcache flush step. Also, it updates all users
to do the flush as the last chance.
Signed-off-by: Tomasz Nowicki
---
drivers/iommu/amd_iommu.c
solution is that machines with relatively
small numbers of CPUs may get DAC addresses more frequently for PCI
devices. Please let me know your thoughts.
Tomasz Nowicki (1):
iommu/iova: Make rcache flush optional on IOVA allocation failure
drivers/iommu/amd_iommu.c | 5 +++--
drivers/iomm
Hi Jean,
On 27.02.2017 20:54, Jean-Philippe Brucker wrote:
@@ -1213,17 +1356,59 @@ static void arm_smmu_free_cd_tables(struct
arm_smmu_master_data *master)
__maybe_unused
static int arm_smmu_alloc_cd(struct arm_smmu_master_data *master)
{
+ int ssid;
+ int i, ret;
struct
Hi Jean,
On 27.02.2017 20:54, Jean-Philippe Brucker wrote:
+/*
+ * Returns -ENOSYS if ATS is not supported either by the device or by the SMMU
+ */
+static int arm_smmu_enable_ats(struct arm_smmu_master_data *master)
+{
+ int ret;
+ size_t stu;
+ struct pci_dev *pdev;
+ s
On 26.04.2017 12:08, Jean-Philippe Brucker wrote:
On 26/04/17 07:53, Tomasz Nowicki wrote:
+mutex_lock(&device->tasks_lock);
+list_for_each_entry(vfio_task, &device->tasks, list) {
+if (vfio_task->pasid != svm.pasid)
+continue;
+
On 27.02.2017 20:54, Jean-Philippe Brucker wrote:
Let the process that owns the device create an address space bond on
behalf of another process. We add a pid argument to the BIND_TASK ioctl,
allowing the caller to bind a foreign task. The expected program flow in
this case is:
* Process A creat
Hi Jean,
On 27.02.2017 20:54, Jean-Philippe Brucker wrote:
Add two new ioctl for VFIO devices. VFIO_DEVICE_BIND_TASK creates a bond
between a device and a process address space, identified by a
device-specific ID named PASID. This allows the device to target DMA
transactions at the process virtu
Hi Robin,
On 25.01.2017 18:35, Robin Murphy wrote:
Hi Tomasz,
On 25/01/17 17:17, Tomasz Nowicki wrote:
Hi Sricharan,
On 23.01.2017 17:18, Sricharan R wrote:
From: Robin Murphy
In preparation for some upcoming cleverness, rework the control flow in
of_iommu_configure() to minimise
On 23.01.2017 17:18, Sricharan R wrote:
From: Robin Murphy
Now that the appropriate ordering is enforced via profe-deferral of
masters in core code, rip it all out and bask in the simplicity.
Acked-by: Will Deacon
Signed-off-by: Robin Murphy
[Sricharan: Rebased on top of ACPI IORT SMMU serie
Hi Sricharan,
On 23.01.2017 17:18, Sricharan R wrote:
From: Robin Murphy
In preparation for some upcoming cleverness, rework the control flow in
of_iommu_configure() to minimise duplication and improve the propogation
of errors. It's also as good a time as any to switch over from the
now-just-
On 19.01.2017 11:57, Aleksey Makarov wrote:
Hi Tomasz,
On 01/19/2017 11:55 AM, Tomasz Nowicki wrote:
Hi Aleksey,
On 17.01.2017 16:14, Aleksey Makarov wrote:
Enable the Extended Stream ID feature when available.
This patch on top of series "KVM PCIe/MSI passthrough on ARM/ARM64
and
device because the stream ID is
out of range. This is the case for all devices connected as external
endpoints on ThunderX.
To fix above issue enable the Extended Stream ID optional feature when
available.
Please add my:
Reviewed-by: Tomasz Nowicki
Tested-by: Tomasz Nowicki
Thank
, let's correct this.
Signed-off-by: Eric Auger
Acked-by: Will Deacon
For patches [15-18]:
Reviewed-by: Tomasz Nowicki
Thanks,
Tomasz
---
v7 -> v8:
- added Will's A-b
---
drivers/iommu/arm-smmu-v3.c | 2 --
drivers/iommu/arm-smmu.c| 2 --
2 files changed, 4 deletions(-)
On 17.01.2017 15:06, Tomasz Nowicki wrote:
On 17.01.2017 14:53, Auger Eric wrote:
Hi Tomasz,
On 17/01/2017 14:40, Tomasz Nowicki wrote:
On 11.01.2017 10:41, Eric Auger wrote:
This new function checks whether all MSI irq domains
implement IRQ remapping. This is useful to understand
whether
On 11.01.2017 10:41, Eric Auger wrote:
Now we have a flag value indicating an IRQ domain implements MSI,
let's set it on msi_create_irq_domain().
Signed-off-by: Eric Auger
Reviewed-by: Marc Zyngier
Reviewed-by: Tomasz Nowicki
Thanks,
Tomasz
---
v7 -> v8
- Added Marc's
check all MSI irq domains have
MSI remapping support when assessing the safety of IRQ assignment
to a guest.
irq_domain_hierarchical_is_msi_remap() allows to check if an
irq domain or any parent implements MSI remapping.
Signed-off-by: Eric Auger
Reviewed-by: Marc Zyngier
Reviewed-by: Tomasz
sysfs.
Signed-off-by: Eric Auger
Acked-by: Will Deacon
Reviewed-by: Tomasz Nowicki
Thanks,
Tomasz
---
v7 -> v8:
- added Will's A-b
v4: creation
---
drivers/iommu/arm-smmu-v3.c | 28
1 file changed, 28 insertions(+)
diff --git a/drivers/iommu/arm-smm
On 17.01.2017 14:53, Auger Eric wrote:
Hi Tomasz,
On 17/01/2017 14:40, Tomasz Nowicki wrote:
On 11.01.2017 10:41, Eric Auger wrote:
This new function checks whether all MSI irq domains
implement IRQ remapping. This is useful to understand
whether VFIO passthrough is safe with respect to
On 11.01.2017 10:41, Eric Auger wrote:
This new function checks whether all MSI irq domains
implement IRQ remapping. This is useful to understand
whether VFIO passthrough is safe with respect to interrupts.
On ARM typically an MSI controller can sit downstream
to the IOMMU without preventing VFI
On 11.01.2017 10:41, Eric Auger wrote:
The get() populates the list with the MSI IOVA reserved window.
At the moment an arbitray MSI IOVA window is set at 0x800
of size 1MB. This will allow to report those info in iommu-group
sysfs.
Signed-off-by: Eric Auger
Reviewed-by: Tomasz Nowicki
: Eric Auger
Reviewed-by: Tomasz Nowicki
Thanks,
Tomasz
---
v6 -> v7:
- avoid merge of regions of different type
v3 -> v4:
- take the iommu_group lock in iommu_get_group_resv_regions
- the list now is sorted and overlaps are checked
NOTE:
- we do not move list elements from device to
On 11.01.2017 10:41, Eric Auger wrote:
As we introduced new reserved region types which do not require
mapping, let's make sure we only map direct mapped regions.
Signed-off-by: Eric Auger
Reviewed-by: Tomasz Nowicki
Thanks,
Tomasz
---
v3 -> v4:
- use region's type and
On 11.01.2017 10:41, Eric Auger wrote:
Introduce a new helper serving the purpose to allocate a reserved
region. This will be used in iommu driver implementing reserved
region callbacks.
Signed-off-by: Eric Auger
Reviewed-by: Tomasz Nowicki
Thanks,
Tomasz
---
v3 -> v4:
-
address space or because
they are not translated by the IOMMU and need special handling)
So let's rename the struct and also the callbacks.
Signed-off-by: Eric Auger
Acked-by: Robin Murphy
Reviewed-by: Tomasz Nowicki
Thanks,
Tomasz
---
v3 -> v4:
- add Robin's A-b
---
space to a managed cookie, and extend the mapping
routine to implement a trivial linear allocator in such cases, to avoid
the needless overhead of a full-blown IOVA domain.
Signed-off-by: Robin Murphy
Reviewed-by: Tomasz Nowicki
Thanks,
Tomasz
---
drivers/iommu/dma-iommu.c
My apologise for not adding 2nd version info of this patch to mail subject.
Thanks,
Tomasz
On 16.01.2017 08:16, Tomasz Nowicki wrote:
The goal of erratum #27704 workaround was to make sure that ASIDs and VMIDs
are unique across all SMMU instances on affected Cavium systems.
Currently, the
ASIDs consistently for all SMMU instances.
Signed-off-by: Tomasz Nowicki
Reviewed-by: Robin Murphy
Reviewed-by: Tirumalesh Chalamarla
---
drivers/iommu/arm-smmu.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c
index a60cded..476fab9
with internal 10G VNIC and Intel IXGBE
NIC. Please feel free to add my:
Tested-by: Tomasz Nowicki
Thanks,
Tomasz
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https://lists.linuxfoundation.org/mailman/listinfo/iommu
On 12.01.2017 07:41, Tomasz Nowicki wrote:
On 11.01.2017 13:19, Robin Murphy wrote:
On 11/01/17 11:51, Tomasz Nowicki wrote:
The goal of erratum #27704 workaround was to make sure that ASIDs and
VMIDs
are unique across all SMMU instances on affected Cavium systems.
Currently, the workaround
On 11.01.2017 13:19, Robin Murphy wrote:
On 11/01/17 11:51, Tomasz Nowicki wrote:
The goal of erratum #27704 workaround was to make sure that ASIDs and VMIDs
are unique across all SMMU instances on affected Cavium systems.
Currently, the workaround code partitions ASIDs and VMIDs by increasing
rt for stage-1
AArch64 contexts for Cavium SMMUv2 model so that we use ASIDs consistently.
Signed-off-by: Tomasz Nowicki
---
drivers/iommu/arm-smmu.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c
index a60cded..ae8f059 100644
--- a/drivers
/lpieralisi/linux.git
acpi/iort-smmu-v7
Tested on Juno and FVP models for ARM SMMU v1 and v3 probing path.
For all series:
Reviewed-by: Tomasz Nowicki
Thanks,
Tomasz
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passthrough mode successfully on ACPI host using ThunderX 1-socket board.
Also, for my tests I used Eric's patches:
https://github.com/eauger/linux/commits/v4.9-rc3-reserved-rfc-v2
Including bug fix above:
Tested-by: Tomasz Nowicki for all series.
+
+ if (!IORT_IRQ_MASK(glb_irq[1])) /*
On 07.06.2016 15:31, Lorenzo Pieralisi wrote:
+static int __get_pci_rid(struct pci_dev *pdev, u16 alias, void *data)
+{
+ u32 *rid = data;
+
+ *rid = alias;
+ return 0;
+}
+
+/**
+ * iort_iommu_configure - Set-up IOMMU configuration for a device.
+ *
+ * @dev: device to configur
On 17.05.2016 10:07, Tomasz Nowicki wrote:
Hi Lorenzo,
On 14.04.2016 19:25, Lorenzo Pieralisi wrote:
On DT based systems, the of_dma_configure() API implements DMA
configuration
for a given device. On ACPI systems an API equivalent to
of_dma_configure()
is missing which implies that it is
on ARM systems and leaving behaviour unchanged
for all other arches.
Signed-off-by: Lorenzo Pieralisi
Cc: Bjorn Helgaas
Cc: Robin Murphy
Cc: Tomasz Nowicki
Cc: Joerg Roedel
Cc: "Rafael J. Wysocki"
---
drivers/acpi/glue.c | 4 +--
drivers/acpi/iort.
On 16.05.2016 17:15, Tomasz Nowicki wrote:
On 18.04.2016 12:43, Robin Murphy wrote:
On 15/04/16 19:29, Timur Tabi wrote:
On Thu, Apr 14, 2016 at 12:25 PM, Lorenzo Pieralisi
wrote:
+void acpi_dma_configure(struct device *dev, enum dev_dma_attr attr)
+{
+ struct iommu_ops *iommu
On 18.04.2016 12:43, Robin Murphy wrote:
On 15/04/16 19:29, Timur Tabi wrote:
On Thu, Apr 14, 2016 at 12:25 PM, Lorenzo Pieralisi
wrote:
+void acpi_dma_configure(struct device *dev, enum dev_dma_attr attr)
+{
+ struct iommu_ops *iommu;
+
+ iommu = iort_iommu_configure(dev);
+
+
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