From: Kuppuswamy Sathyanarayanan
Return the Page Aligned Request bit in the ATS Capability Register.
As per PCIe spec r4.0, sec 10.5.1.2, if the Page Aligned Request bit is
set, it indicates the Untranslated Addresses generated by the device are
always aligned to a 4096 byte boundary.
An IOMMU
From: Kuppuswamy Sathyanarayanan
As per Intel vt-d specification, Rev 3.0 (section 7.5.1.1, title "Page
Request Descriptor"), Intel IOMMU page request descriptor only uses
bits[63:12] of the page address. Hence Intel IOMMU driver would only
permit devices that advertise they would only send Page
From: Kuppuswamy Sathyanarayanan
As per Intel vt-d specification, Rev 3.0 (section 7.5.1.1, title
"Page Request Descriptor"), Intel IOMMU page request descriptor
only uses bits[63:12] of the Page Address. Hence its required to
enforce that the device will only send page request with
page-aligned
From: Kuppuswamy Sathyanarayanan
In Intel IOMMU, if the Page Request Queue (PRQ) is full, it will
automatically respond to the device with a success message as a keep
alive. And when sending the success message, IOMMU will include PASID in
the Response Message when the Page Request has a PASID in
From: Kuppuswamy Sathyanarayanan
Return the PRG Response PASID Required bit in the Page Request
Status Register.
As per PCIe spec r4.0, sec 10.5.2.3, if this bit is Set, the device
expects a PASID TLP Prefix on PRG Response Messages when the
corresponding Page Requests had a PASID TLP Prefix. If
From: Kuppuswamy Sathyanarayanan
Intel IOMMU responds automatically when receiving page-requests from
a PCIe endpoint and the page-request queue is full and it cannot accept
any more page-requests. When it auto-responds to page-requests with a
success to the endpoint, it automatically responds wi
ommu@lists.linux-foundation.org
https://lists.linuxfoundation.org/mailman/listinfo/iommu
--
Sathyanarayanan Kuppuswamy
Linux kernel developer
___
iommu mailing list
iommu@lists.linux-foundation.org
https://lists.linuxfoundation.org/mailman/listinfo/iommu
From: Kuppuswamy Sathyanarayanan
Intel IOMMU responds automatically when receiving page-requests from
a PCIe endpoint and the page-request queue is full and it cannot accept
any more page-requests. When it auto-responds to page-requests with a
success to the endpoint, it automatically responds wi
From: Kuppuswamy Sathyanarayanan
Return the PRG Response PASID Required bit in the Page Request
Status Register.
As per PCIe spec r4.0, sec 10.5.2.3, if this bit is Set then the device
expects a PASID TLP Prefix on PRG Response Messages when the
corresponding Page Requests had a PASID TLP Prefix
From: Kuppuswamy Sathyanarayanan
In Intel IOMMU, if the Page Request Queue (PRQ) is full, it will
automatically respond to the device with a success message as a keep
alive. And when sending the success message, IOMMU will include PASID in
the Response Message when the Page Request has a PASID in
| 2 ++
include/uapi/linux/pci_regs.h | 1 +
4 files changed, 28 insertions(+)
--
Sathyanarayanan Kuppuswamy
Linux kernel developer
___
iommu mailing list
iommu@lists.linux-foundation.org
https://lists.linuxfoundation.org/mailman/listinfo/iommu
From: Kuppuswamy Sathyanarayanan
As per Intel vt-d specification, Rev 3.0 (section 7.5.1.1, title "Page
Request Descriptor"), Intel IOMMU page request descriptor only uses
bits[63:12] of the page address. Hence Intel IOMMU driver would only
permit devices that advertise they would only send page
From: Kuppuswamy Sathyanarayanan
As per Intel vt-d specification, Rev 3.0 (section 7.5.1.1, title
"Page Request Descriptor"), Intel IOMMU page request descriptor
only uses bits[63:12] of the Page Address. Hence its required to
enforce that the device will only send page request with
page-aligned
From: Kuppuswamy Sathyanarayanan
Return the Page Aligned Request bit in the ATS Capability Register.
As per PCIe spec r4.0, sec 10.5.1.2, If Page Aligned Request bit is
set, then it indicates the Untranslated Addresses generated by the
device are alwayis always aligned to a 4096 byte boundary.
From: Kuppuswamy Sathyanarayanan
As per Intel vt-d specification, Rev 3.0 (section 7.5.1.1, title "Page Request
Descriptor"), Intel IOMMU Page Request Descriptor only provides bits[63:12] of
the page address. Hence its required to enforce that the device will only send
page request with page-a
On 2/11/19 11:15 AM, Raj, Ashok wrote:
On Fri, Feb 08, 2019 at 11:49:55PM -0500, Sinan Kaya wrote:
On 2/8/2019 8:02 PM, sathyanarayanan kuppuswamy wrote:
This means that you should probably have some kind of version check
here.
There is no version field in ATS v1.0 spec. Also, If I follow
On 2/7/19 5:58 PM, Sinan Kaya wrote:
On 2/7/2019 5:16 PM, sathyanarayanan kuppuswamy wrote:
If I remember this right, aligned request is only supported on ATS v1.1
but not supported on v1.0.
Its added in v1.1.
This means that you should probably have some kind of version check
here
k the spec?
--
Sathyanarayanan Kuppuswamy
Linux kernel developer
___
iommu mailing list
iommu@lists.linux-foundation.org
https://lists.linuxfoundation.org/mailman/listinfo/iommu
o expose whats
currently supported clearly.
Yes, we're going
to want to hook up a way to pass the PRI to the right place... but why
add *another* thing that's just going to have to be fixed, by reverting
this patch?
--
Sathyanarayanan Kuppuswamy
Linux kernel developer
__
ne PCI_ATS_CTRL 0x06/* ATS Control Register */
#define PCI_ATS_CTRL_ENABLE 0x8000 /* ATS Enable */
#define PCI_ATS_CTRL_STU(x) ((x) & 0x1f)/* Smallest Translation
Unit */
--
2.20.1
--
Sathyanarayanan Kuppuswamy
Linux kernel developer
___
From: Kuppuswamy Sathyanarayanan
Intel IOMMU Page Request Services (PRS) only works with devices which
supports/uses PASID. So enable PRI only if the device also enables
PASID support. For more details, Please check the implementation of PRQ
handler(prq_event_thread()) in intel-svm driver.
Cc: J
From: Kuppuswamy Sathyanarayanan
In Intel IOMMU, if the Page Request Queue (PRQ) is full, it will
automatically respond to the device with a success message as a keep
alive. And when sending the success message, IOMMU will include PASID in
the response message when the page request has a PASID in
From: Kuppuswamy Sathyanarayanan
Add a new function to return the status of PRG response PASID
required bit in PRI status register. This function will be used by
drivers like IOMMU, if it is required to enforce the PASID required for
page-group responses.
Cc: Ashok Raj
Cc: Jacob Pan
Cc: Keith
From: Kuppuswamy Sathyanarayanan
As per Intel vt-d specification, Rev 3.0 (section 7.5.1.1, title
"Page Request Descriptor"), Intel IOMMU page request descriptor
only uses bits[63:12] of the page address. Hence its required to
enforce that the device will only send page request with
page-aligned
From: Kuppuswamy Sathyanarayanan
Intel IOMMU responds automatically when receiving page-requests from
a PCIe endpoint and the page-request queue is full and it cannot accept
any more page-requests. When it auto-responds to page-requests with a
success to the endpoint, it automatically responds wi
From: Kuppuswamy Sathyanarayanan
Add a new function to return the status of ATS page aligned request
bit in ATS capability register. This function will be used by
drivers like IOMMU, if it is required to enforce page-aligned
requests in ATS.
Cc: Ashok Raj
Cc: Jacob Pan
Cc: Keith Busch
Suggest
From: Kuppuswamy Sathyanarayanan
As per Intel vt-d specification, Rev 3.0 (section 7.5.1.1, title "Page
Request Descriptor"), Intel IOMMU page request descriptor only uses
bits[63:12] of the page address. Hence Intel IOMMU driver would only
permit devices that advertise they would only send page
27 matches
Mail list logo
