Re: [PATCH] iommu/vt-d: Avoid write-tearing on PTE clear

On Sat, May 21, 2016 at 02:51:23AM -0700, Nadav Amit wrote: > When a PTE is cleared, the write may be teared or perform by multiple > writes. In addition, in 32-bit kernel, writes are currently performed > using a single 64-bit write, which does not guarantee order. > > The byte-code right now

Re: [PATCH] iommu/vt-d: Avoid write-tearing on PTE clear

Ping? Nadav Amit wrote: > When a PTE is cleared, the write may be teared or perform by multiple > writes. In addition, in 32-bit kernel, writes are currently performed > using a single 64-bit write, which does not guarantee order. > > The byte-code right now does not seem to

[PATCH] iommu/vt-d: Avoid write-tearing on PTE clear

When a PTE is cleared, the write may be teared or perform by multiple writes. In addition, in 32-bit kernel, writes are currently performed using a single 64-bit write, which does not guarantee order. The byte-code right now does not seem to cause a problem, but it may still occur in theory.