On Wed, 19 Sep 2018 22:25:03 +
"Eads, Gage" wrote:
> > This looks good and also addresses Alan's concern that don't
> > silently hide under the rug for all devices. We'll also queue it
> > for testing just to confirm and keep you posted.
> >
> > Reviewed-by: Ashok Raj
> >
>
> Hi Alex,
>
> This looks good and also addresses Alan's concern that don't silently hide
> under
> the rug for all devices. We'll also queue it for testing just to confirm and
> keep
> you posted.
>
> Reviewed-by: Ashok Raj
>
Hi Alex,
I've confirmed that the patch works as intended for the 8086:270c dev
Hi Alex
On Tue, Sep 18, 2018 at 09:59:57PM -0600, Alex Williamson wrote:
> On Wed, 12 Sep 2018 10:46:19 -0700
> "Raj, Ashok" wrote:
>
> > On Thu, Aug 09, 2018 at 01:44:17PM -0600, Alex Williamson wrote:
> > > On Thu, 9 Aug 2018 12:37:06 -0700
> > > Ashok Raj wrote:
> > >
> > > > PCI_INTERR
On Wed, 12 Sep 2018 10:46:19 -0700
"Raj, Ashok" wrote:
> On Thu, Aug 09, 2018 at 01:44:17PM -0600, Alex Williamson wrote:
> > On Thu, 9 Aug 2018 12:37:06 -0700
> > Ashok Raj wrote:
> >
> > > PCI_INTERRUPT_PIN should always read 0 for SRIOV Virtual
> > > Functions.
> > >
> > > Some SRIOV de
On Thu, Aug 09, 2018 at 01:44:17PM -0600, Alex Williamson wrote:
> On Thu, 9 Aug 2018 12:37:06 -0700
> Ashok Raj wrote:
>
> > PCI_INTERRUPT_PIN should always read 0 for SRIOV Virtual Functions.
> >
> > Some SRIOV devices have some bugs in RTL and VF's end up reading 1
> > instead of 0 for the
On Fri, Aug 10, 2018 at 05:48:36PM +0100, Alan Cox wrote:
> > The hardware isn't public yet, so can't talk about it :-(. Once this patch
> > gets
> > merged, will let the OSV engagement folks drive it for inclusions. We
> > could mark this for stable, but i would rather wait until we know the
>
> The hardware isn't public yet, so can't talk about it :-(. Once this patch
> gets
> merged, will let the OSV engagement folks drive it for inclusions. We
> could mark this for stable, but i would rather wait until we know the
> timeline when they are expecting it to be in. It shouldn't break
On Thu, Aug 09, 2018 at 01:44:17PM -0600, Alex Williamson wrote:
> On Thu, 9 Aug 2018 12:37:06 -0700
> Ashok Raj wrote:
>
> > PCI_INTERRUPT_PIN should always read 0 for SRIOV Virtual Functions.
> >
> > Some SRIOV devices have some bugs in RTL and VF's end up reading 1
> > instead of 0 for the
On Thu, 9 Aug 2018 12:37:06 -0700
Ashok Raj wrote:
> PCI_INTERRUPT_PIN should always read 0 for SRIOV Virtual Functions.
>
> Some SRIOV devices have some bugs in RTL and VF's end up reading 1
> instead of 0 for the PIN.
Hi Ashok,
One question, can we identify which VFs are known to have this
PCI_INTERRUPT_PIN should always read 0 for SRIOV Virtual Functions.
Some SRIOV devices have some bugs in RTL and VF's end up reading 1
instead of 0 for the PIN.
Since this is a spec required value, rather than having a device specific
quirk, we could fix it permanently in vfio.
Reworked suggest
10 matches
Mail list logo
