On Fri, Feb 14, 2020 at 06:44:51PM +0800, Adrian Huang wrote:
> From: Adrian Huang
>
> The SPA of the GCR3 table root pointer[51:31] masks 20 bits. However,
> this requires 21 bits (Please see the AMD IOMMU specification).
> This leads to the potential failure when the bit 51 of SPA of
> the
From: Adrian Huang
The SPA of the GCR3 table root pointer[51:31] masks 20 bits. However,
this requires 21 bits (Please see the AMD IOMMU specification).
This leads to the potential failure when the bit 51 of SPA of
the GCR3 table root pointer is 1'.
Signed-off-by: Adrian Huang
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