On 19/02/18 02:51, Rob Herring wrote:
[...]
>> +- pasid-bits: Some masters support multiple address spaces for DMA, by
>> + tagging DMA transactions with an address space identifier. By default,
>> + this is 0, which means that the device only has one address space.
>
> So 3 would mean 8 address
On Mon, Feb 12, 2018 at 06:33:26PM +, Jean-Philippe Brucker wrote:
> On ARM systems, some platform devices behind an IOMMU may support stall
> and PASID features. Stall is the ability to recover from page faults and
> PASID offers multiple process address spaces to the device. Together they
> a
On ARM systems, some platform devices behind an IOMMU may support stall
and PASID features. Stall is the ability to recover from page faults and
PASID offers multiple process address spaces to the device. Together they
allow to do paging with a device. Let the firmware tell us when a device
support
