Hi Jon,
Charles Garcia-Tobin has confirmed that the new IORT spec includes Cavium
ThunderX model number.
I have resubmitted patches based on IORT model number.
https://www.spinics.net/lists/arm-kernel/msg579511.html
Thank you,
Geetha.
On Fri, May 5, 2017 at 5:06 AM, Jon Masters wrote:
> On 0
On 05/03/2017 05:47 AM, Will Deacon wrote:
> Hi Geetha,
>
> On Tue, May 02, 2017 at 12:01:15PM +0530, Geetha Akula wrote:
>> SMMU_IIDR register is broken on T99, that the reason we are using MIDR.
>
> Urgh, that's unfortunate. In what way is it broken?
>
>> If using MIDR is not accepted, can we
Hi Will,
We will resubmit the patches based on IORT.
Thank you,
Geetha.
On Wed, May 3, 2017 at 3:17 PM, Will Deacon wrote:
> Hi Geetha,
>
> On Tue, May 02, 2017 at 12:01:15PM +0530, Geetha Akula wrote:
>> SMMU_IIDR register is broken on T99, that the reason we are using MIDR.
>
> Urgh, that's
Hi Geetha,
On Tue, May 02, 2017 at 12:01:15PM +0530, Geetha Akula wrote:
> SMMU_IIDR register is broken on T99, that the reason we are using MIDR.
Urgh, that's unfortunate. In what way is it broken?
> If using MIDR is not accepted, can we enable errata based on SMMU resource
> size?
> some thin
Hi Will,
SMMU_IIDR register is broken on T99, that the reason we are using MIDR.
If using MIDR is not accepted, can we enable errata based on SMMU resource size?
some thing like below.
static bool page0_reg_only = false;
+static unsigned long arm_smmu_resource_size(void)
+{
+ if (page0_reg_
On Thu, Apr 27, 2017 at 05:42:37PM +0100, Mark Rutland wrote:
> On Thu, Apr 27, 2017 at 05:16:23PM +0530, Geetha sowjanya wrote:
> > + /*
> > +* Override the size, for Cavium CN99xx implementations
> > +* which doesn't support the page 1 SMMU register space.
> > +*/
> > + cpu_model
On Thu, Apr 27, 2017 at 05:16:23PM +0530, Geetha sowjanya wrote:
> + /*
> + * Override the size, for Cavium CN99xx implementations
> + * which doesn't support the page 1 SMMU register space.
> + */
> + cpu_model = read_cpuid_id() & MIDR_CPU_MODEL_MASK;
> + if (cpu_model =
From: Linu Cherian
Cavium 99xx SMMU implementation doesn't support page 1 register space.
Based on silicon id, ARM_SMMU_PAGE0_REGS_ONLY macro is set as an errata
workaround.
This macro when set, replaces all page 1 offsets used for
EVTQ_PROD/CONS, PRIQ_PROD/CONS register access with page 0 offs
