It is possible that PCI device supports 64-bit DMA addressing,
and thus it's driver sets device's dma_mask to DMA_BIT_MASK(64),
however PCI host bridge may have limitations on the inbound
transaction addressing.
This is particularly problematic on ARM/ARM64 SOCs where the
IOMMU (i.e. SMMU) trans
It is possible that PCI device supports 64-bit DMA addressing,
and thus it's driver sets device's dma_mask to DMA_BIT_MASK(64),
however PCI host bridge may have limitations on the inbound
transaction addressing.
This is particularly problematic on ARM/ARM64 SOCs where the
IOMMU (i.e. SMMU) trans
It is possible that PCI device supports 64-bit DMA addressing,
and thus it's driver sets device's dma_mask to DMA_BIT_MASK(64),
however PCI host bridge may have limitations on the inbound
transaction addressing.
This is particularly problematic on ARM/ARM64 SOCs where the
IOMMU (i.e. SMMU) trans
