[PATCH v2 07/19] iommu/mediatek: Add REG_MMU_WR_LEN reg define prepare for mt6779

[Chao Hao]

When some platforms(ex:later mt6779) define has_wr_len variable,
we need to set REG_MMU_WR_LEN to improve performance. So we add
REG_MMU_WR_LEN register define in this patch.

Signed-off-by: Chao Hao <chao....@mediatek.com>
---
 drivers/iommu/mtk_iommu.c | 11 +++++++++++
 drivers/iommu/mtk_iommu.h |  2 ++
 2 files changed, 13 insertions(+)

diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c
index 5de13ab1094e..ad5690350d6a 100644
--- a/drivers/iommu/mtk_iommu.c
+++ b/drivers/iommu/mtk_iommu.c
@@ -44,6 +44,8 @@
 
 #define REG_MMU_MISC_CTRL                      0x048
 #define REG_MMU_DCM_DIS                                0x050
+#define REG_MMU_WR_LEN                         0x054
+#define F_MMU_WR_THROT_DIS                     (BIT(5) |  BIT(21))
 
 #define REG_MMU_CTRL_REG                       0x110
 #define F_MMU_TF_PROT_TO_PROGRAM_ADDR          (2 << 4)
@@ -595,6 +597,13 @@ static int mtk_iommu_hw_init(const struct mtk_iommu_data 
*data)
        }
        writel_relaxed(0, data->base + REG_MMU_DCM_DIS);
 
+       if (data->plat_data->has_wr_len) {
+               /* write command throttling mode */
+               regval = readl_relaxed(data->base + REG_MMU_WR_LEN);
+               regval &= ~F_MMU_WR_THROT_DIS;
+               writel_relaxed(regval, data->base + REG_MMU_WR_LEN);
+       }
+
        if (data->plat_data->reset_axi)
                writel_relaxed(0, data->base + REG_MMU_MISC_CTRL);
 
@@ -743,6 +752,7 @@ static int __maybe_unused mtk_iommu_suspend(struct device 
*dev)
        struct mtk_iommu_suspend_reg *reg = &data->reg;
        void __iomem *base = data->base;
 
+       reg->wr_len = readl_relaxed(base + REG_MMU_WR_LEN);
        reg->standard_axi_mode = readl_relaxed(base +
                                               REG_MMU_MISC_CTRL);
        reg->dcm_dis = readl_relaxed(base + REG_MMU_DCM_DIS);
@@ -768,6 +778,7 @@ static int __maybe_unused mtk_iommu_resume(struct device 
*dev)
                dev_err(data->dev, "Failed to enable clk(%d) in resume\n", ret);
                return ret;
        }
+       writel_relaxed(reg->wr_len, base + REG_MMU_WR_LEN);
        writel_relaxed(reg->standard_axi_mode,
                       base + REG_MMU_MISC_CTRL);
        writel_relaxed(reg->dcm_dis, base + REG_MMU_DCM_DIS);
diff --git a/drivers/iommu/mtk_iommu.h b/drivers/iommu/mtk_iommu.h
index d4495230c6e7..0623f199e96f 100644
--- a/drivers/iommu/mtk_iommu.h
+++ b/drivers/iommu/mtk_iommu.h
@@ -25,6 +25,7 @@ struct mtk_iommu_suspend_reg {
        u32                             int_main_control;
        u32                             ivrp_paddr;
        u32                             vld_pa_rng;
+       u32                             wr_len;
 };
 
 enum mtk_iommu_plat {
@@ -43,6 +44,7 @@ struct mtk_iommu_plat_data {
        bool                has_sub_comm[2];
        bool                has_vld_pa_rng;
        bool                reset_axi;
+       bool                has_wr_len;
        u32                 m4u1_mask;
        u32                 inv_sel_reg;
        unsigned char       larbid_remap[2][MTK_LARB_NR_MAX];
-- 
2.18.0
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