On Mon, Feb 11, 2019 at 01:44:34PM -0800,
sathyanarayanan.kuppusw...@linux.intel.com wrote:
> From: Kuppuswamy Sathyanarayanan
>
> Return the Page Aligned Request bit in the ATS Capability Register.
>
> As per PCIe spec r4.0, sec 10.5.1.2, If Page Aligned Request bit is
> set, then it
From: Kuppuswamy Sathyanarayanan
Return the Page Aligned Request bit in the ATS Capability Register.
As per PCIe spec r4.0, sec 10.5.1.2, If Page Aligned Request bit is
set, then it indicates the Untranslated Addresses generated by the
device are alwayis always aligned to a 4096 byte boundary.
