On 26/02/18 18:05, Will Deacon wrote:
On Thu, Dec 14, 2017 at 04:58:53PM +, Robin Murphy wrote:
Stage 1 input addresses are effectively 64-bit in SMMUv3 anyway, so
really all that's involved is letting io-pgtable know the appropriate
upper bound for T0SZ.
Tested-by: Nate Watterson
Signed-o
On Thu, Dec 14, 2017 at 04:58:53PM +, Robin Murphy wrote:
> Stage 1 input addresses are effectively 64-bit in SMMUv3 anyway, so
> really all that's involved is letting io-pgtable know the appropriate
> upper bound for T0SZ.
>
> Tested-by: Nate Watterson
> Signed-off-by: Robin Murphy
> ---
>
Stage 1 input addresses are effectively 64-bit in SMMUv3 anyway, so
really all that's involved is letting io-pgtable know the appropriate
upper bound for T0SZ.
Tested-by: Nate Watterson
Signed-off-by: Robin Murphy
---
v2: No change
drivers/iommu/arm-smmu-v3.c | 8
1 file changed, 8 i
