On Wed, Sep 24, 2014 at 10:21:23AM +0100, Will Deacon wrote:
Some IOMMUs, such as the ARM SMMU, support two stages of translation.
The idea behind such a scheme is to allow a guest operating system to
use the IOMMU for DMA mappings in the first stage of translation, with
the hypervisor then
On Thu, Sep 25, 2014 at 03:32:33PM +0100, Joerg Roedel wrote:
On Wed, Sep 24, 2014 at 10:21:23AM +0100, Will Deacon wrote:
Some IOMMUs, such as the ARM SMMU, support two stages of translation.
The idea behind such a scheme is to allow a guest operating system to
use the IOMMU for DMA
Some IOMMUs, such as the ARM SMMU, support two stages of translation.
The idea behind such a scheme is to allow a guest operating system to
use the IOMMU for DMA mappings in the first stage of translation, with
the hypervisor then installing mappings in the second stage to provide
isolation of the
