On Tue, Aug 17, 2021 at 11:28 AM Atish Patra wrote:
>
> On Mon, Aug 16, 2021 at 6:37 PM Guo Ren wrote:
> >
> > 1
> >
> > On Thu, Jul 29, 2021 at 2:19 PM Atish Patra wrote:
> > >
> > > On Wed, Jul 28, 2021 at 9:30 PM Palmer Dabbelt wrote:
> > > >
> > > > On Fri, 23 Jul 2021 14:40:26 PDT
On Mon, Aug 16, 2021 at 6:37 PM Guo Ren wrote:
>
> 1
>
> On Thu, Jul 29, 2021 at 2:19 PM Atish Patra wrote:
> >
> > On Wed, Jul 28, 2021 at 9:30 PM Palmer Dabbelt wrote:
> > >
> > > On Fri, 23 Jul 2021 14:40:26 PDT (-0700), Atish Patra wrote:
> > > > RISC-V privilege specification doesn't
1
On Thu, Jul 29, 2021 at 2:19 PM Atish Patra wrote:
>
> On Wed, Jul 28, 2021 at 9:30 PM Palmer Dabbelt wrote:
> >
> > On Fri, 23 Jul 2021 14:40:26 PDT (-0700), Atish Patra wrote:
> > > RISC-V privilege specification doesn't define an IOMMU or any method
> > > modify
> > > PMA attributes or
On Fri, 23 Jul 2021 14:40:26 PDT (-0700), Atish Patra wrote:
RISC-V privilege specification doesn't define an IOMMU or any method modify
PMA attributes or PTE entries to allow non-coherent mappings yet. In
the beginning, this approach was adopted assuming that most of the RISC-V
platforms would
On Wed, Jul 28, 2021 at 9:30 PM Palmer Dabbelt wrote:
>
> On Fri, 23 Jul 2021 14:40:26 PDT (-0700), Atish Patra wrote:
> > RISC-V privilege specification doesn't define an IOMMU or any method modify
> > PMA attributes or PTE entries to allow non-coherent mappings yet. In
> > the beginning, this
RISC-V privilege specification doesn't define an IOMMU or any method modify
PMA attributes or PTE entries to allow non-coherent mappings yet. In
the beginning, this approach was adopted assuming that most of the RISC-V
platforms would support full cache-coherent IO. Here is excerpt from the
priv
