Thierry Reding writes:
> diff --git a/include/dt-bindings/memory/tegra124-mc.h
> b/include/dt-bindings/memory/tegra124-mc.h
> new file mode 100644
> index ..6b1617ce022f
> --- /dev/null
> +++ b/include/dt-bindings/memory/tegra124-mc.h
> @@ -0,0 +1,30 @@
> +#ifndef DT_BINDINGS_MEMORY
On 06/26/2014 02:49 PM, Thierry Reding wrote:
> From: Thierry Reding
>
> The memory controller on NVIDIA Tegra124 exposes various knobs that can
> be used to tune the behaviour of the clients attached to it.
>
> Currently this driver sets up the latency allowance registers to the HW
> defaults.
On 06/27/2014 05:15 AM, Thierry Reding wrote:
> On Fri, Jun 27, 2014 at 01:07:04PM +0200, Arnd Bergmann wrote:
>> On Thursday 26 June 2014 22:49:44 Thierry Reding wrote:
>>> +static const struct tegra_mc_client tegra124_mc_clients[] = {
>>> + {
>>> + .id = 0x01,
>>> +
On 06/27/2014 05:08 AM, Thierry Reding wrote:
> On Fri, Jun 27, 2014 at 12:46:38PM +0300, Hiroshi DOyu wrote:
>>
>> Thierry Reding writes:
>>
>>> From: Thierry Reding
>>>
>>> The memory controller on NVIDIA Tegra124 exposes various knobs that can
>>> be used to tune the behaviour of the clients a
On Fri, Jun 27, 2014 at 01:07:04PM +0200, Arnd Bergmann wrote:
> On Thursday 26 June 2014 22:49:44 Thierry Reding wrote:
> > +static const struct tegra_mc_client tegra124_mc_clients[] = {
> > + {
> > + .id = 0x01,
> > + .name = "display0a",
> > + .swg
On Fri, Jun 27, 2014 at 12:46:38PM +0300, Hiroshi DOyu wrote:
>
> Thierry Reding writes:
>
> > From: Thierry Reding
> >
> > The memory controller on NVIDIA Tegra124 exposes various knobs that can
> > be used to tune the behaviour of the clients attached to it.
> >
> > Currently this driver sets
On Thursday 26 June 2014 22:49:44 Thierry Reding wrote:
> +static const struct tegra_mc_client tegra124_mc_clients[] = {
> + {
> + .id = 0x01,
> + .name = "display0a",
> + .swgroup = TEGRA_SWGROUP_DC,
> + .smmu = {
> +
Thierry Reding writes:
> From: Thierry Reding
>
> The memory controller on NVIDIA Tegra124 exposes various knobs that can
> be used to tune the behaviour of the clients attached to it.
>
> Currently this driver sets up the latency allowance registers to the HW
> defaults. Eventually an API shou
Thierry Reding writes:
> * PGP Signed by an unknown key
>
> On Fri, Jun 27, 2014 at 03:41:20PM +0800, Joseph Lo wrote:
>> Hi Thierry,
>>
>> On 06/27/2014 04:49 AM, Thierry Reding wrote:
>> [snip]
>> >+
>> >+#define MC_INTSTATUS 0x000
>> >+#define MC_INT_DECERR_MTS (1 << 16)
>> >+#define MC_IN
On Fri, Jun 27, 2014 at 03:41:20PM +0800, Joseph Lo wrote:
> Hi Thierry,
>
> On 06/27/2014 04:49 AM, Thierry Reding wrote:
> [snip]
> >+
> >+#define MC_INTSTATUS 0x000
> >+#define MC_INT_DECERR_MTS (1 << 16)
> >+#define MC_INT_SECERR_SEC (1 << 13)
> >+#define MC_INT_DECERR_VPR (1 << 12)
> >+#de
Hi Thierry,
On 06/27/2014 04:49 AM, Thierry Reding wrote:
[snip]
+
+#define MC_INTSTATUS 0x000
+#define MC_INT_DECERR_MTS (1 << 16)
+#define MC_INT_SECERR_SEC (1 << 13)
+#define MC_INT_DECERR_VPR (1 << 12)
+#define MC_INT_INVALID_APB_ASID_UPDATE (1 << 11)
+#define MC_INT_INVALID_SMMU_PAGE (
From: Thierry Reding
The memory controller on NVIDIA Tegra124 exposes various knobs that can
be used to tune the behaviour of the clients attached to it.
Currently this driver sets up the latency allowance registers to the HW
defaults. Eventually an API should be exported by this driver (via a
c
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