Just wondering if someone has tried jailhouse and Erika 3 on qemu for arm64? Do
they run fine?
Thanks
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eive the IPI. So the problem is within Erika interrupt
> configuration.
>
> > Hi,
> >
> > On 9/5/18 8:28 PM, Giovani Gracioli wrote:
> > > Yes, I did enable with Erika API.
> >
> > No, I meant if you tried to receive the SGI via Jailhouse inmates. I
&
gic-demo is able to receive the IPI. So the problem is within Erika interrupt
configuration.
> Hi,
>
> On 9/5/18 8:28 PM, Giovani Gracioli wrote:
> > Yes, I did enable with Erika API.
>
> No, I meant if you tried to receive the SGI via Jailhouse inmates. I
> do
Yes, I did enable with Erika API.
s |= CreateTask( &isr_ivshmem, OSEE_TASK_TYPE_ISR2, handle_IRQ, 1U, 1U, 1U,
OSEE_SYSTEM_STACK );
SetISR2Source(isr_ivshmem, i);
gic_enable_irq(i); //this is actually from jailhouse api
Where "i" is the interrupt number. I tried having "i" with 15. Maybe somethi
Hi,
I am playing around IPI among non-root cells (I know it breaks the isolation
among cells, but I would like to understand the steps). I forced a call to
irqchip_set_pending from CPU 3 to CPU 2 in the gic_handle_sgir_write() function:
irqchip_set_pending(per_cpu(2), sgi->id);
sgi->id is 15.
Our work around was forwarding the smc call to the firmware, using the original
code in the Linux firmware.c file. It is not the best solution, but it works.
Maybe the next step is to refine it and have a better integration with
Jailhouse.
Files are attached:
- hypervisor/arch/arm64/traps.c
-
> >
> > Hello,
> >
> > I am interested in inter-cell communication between an ARM linux root cell
> > and the baremetal inmate. I'd like the baremetal to process I/O and write
> > data to a buffer in RAM. On the linux side, I'd like to know when that
> > buffer was full and copy it to a file
ht now) tests whether
reg[0] >> 24 is 0xC2, which is true in this test, and not handled. It seems
that all requests from the r5 driver have the format 0xC0X.
Sorry for the long message and codes, but I think it helps to have an overview
from what is happening.
> On 2018-08-20 15:31, Gi
_hvc?
>
> Giovani
>
> > >
> > > On 2018-08-13 15:15, Giovani Gracioli wrote:
> > > > There is only the root cell. The problem does not happen when the root
> > > > cell is
> > > not loaded.
> > > >
> > > > My un
-08-13 15:15, Giovani Gracioli wrote:
> > > There is only the root cell. The problem does not happen when the root
> > > cell is
> > not loaded.
> > >
> > > My understanding is that the zynqmp_r5_remoteproc driver issues and hvc
> > instructi
Hi Jan,
Yes I am using the latest Xilinx kernel because I need some drivers only
available on it.
> On 2018-08-13 15:15, Giovani Gracioli wrote:
> > There is only the root cell. The problem does not happen when the root cell
> > is not loaded.
> >
> > M
?
> Hi,
>
> On 08/13/2018 03:18 PM, Giovani Gracioli wrote:
> > Yes, that's right. It seems that something that has changed between 0.9.1
> > and master somehow broke the UART when Erika is running.
>
> could you please run git bisect to spot the commit?
>
ter branch.
> >>
> >> I downloaded this one
> >> (https://github.com/siemens/jailhouse/archive/v0.9.1.tar.gz). Will test
> >> and get back to you.
> >>
> >> Giovani
> >>
> >>> Hi Giovani,
> >>>
> >>> On
>
> > > >
> > > > This does not happen when Jailhouse is loaded. Should the flags contain
> > anything else?
> > > >
> > > > Best
> > > > Giovani
> > > >
> > > >> Hi,
> > > >>
> > &g
return the
expected (the R5 is actually running).
> >> Hi,
> >>
> >> On 08/09/2018 06:35 PM, Giovani Gracioli wrote:
> >>> Thanks Ralf.
> >>>
> >>> I updated to the latest version, 0.9.1, and the original problem is gone.
>
Em quinta-feira, 9 de agosto de 2018 19:20:36 UTC-4, Ralf Ramsauer escreveu:
> Hi,
>
> On 08/09/2018 06:35 PM, Giovani Gracioli wrote:
> > Thanks Ralf.
> >
> > I updated to the latest version, 0.9.1, and the original problem is gone.
>
> Great.
>
> &g
> get back to you.
>
> Giovani
>
> > Hi Giovani,
> >
> > On 08/09/2018 10:26 PM, Giovani Gracioli wrote:
> > > Hello,
> > >
> > > I was using Jailhouse version 0.8 with Erika on the ultrascale+ platform.
> > >
> > > I m
Hi Ralf,
Yes, you are right. I cloned the master branch.
I downloaded this one
(https://github.com/siemens/jailhouse/archive/v0.9.1.tar.gz). Will test and get
back to you.
Giovani
> Hi Giovani,
>
> On 08/09/2018 10:26 PM, Giovani Gracioli wrote:
> > Hello,
> >
>
Hello,
I was using Jailhouse version 0.8 with Erika on the ultrascale+ platform.
I migrated to version 0.9.1, but there is no printing on the UART after I start
the Erika cells.
When I run the gic-demo with the zynqmp-zcu102-gic-demo.cell, UART works fine.
I attached both the root and non-root
Not sure the situation of this, but I created a patch that provides PCI support
for arm (Jailhouse version 0.9.1). It is attached.
It is based on the Evidence's code. I tested it on the ultrascale+ (arm64).
It may be useful for some people.
Best
Giovani
> On 2018-04-18 21:52, Giovani
node status.
Failed to get RPU node status.
This does not happen when Jailhouse is loaded. Should the flags contain
anything else?
Best
Giovani
> Hi,
>
> On 08/09/2018 04:26 PM, Giovani Gracioli wrote:
> > Hello,
> >
> > I am running Jailhouse v0.8 on the ultrascal
are 6 different
IPIs in my setup. In the tests I made, the 4 ivshmem devices have individual
interrupt numbers, but the next 2 (shared among non-root cells) use the same
interrupt numbers.
> On 2018-07-30 21:13, Giovani Gracioli wrote:
> > That is because the number of IRQ pins (four)
Hello,
I am running Jailhouse v0.8 on the ultrascale+. I have enabled the root cell
then started the remote R5 processor (using the zynqmp_r5_remoteproc and
rpmsg_user_dev_driver drivers). The R5 communicates to A53 through interrupts
from the remote proc filesystem.
Once I started the R5 cod
Hi Marco,
Thank you for your answer.
We are using the ultrascale+. I am available to help testing and debugging if
needed.
Best
Giovani
> Dear Giovani,
>
> > Is there an implementation of page coloring (cache partitioning) in
> > Jailhouse? Has someone already thought about it?
>
> We at th
Hello
Is there an implementation of page coloring (cache partitioning) in Jailhouse?
Has someone already thought about it?
Thanks
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levels and the second one overwrites this with only one level and a
> hugepage. This case seems unlikely to occur with normal Jailhouse
> reconfigurations. So we may consider dropping the cleanup path in the
> future. It's fixed and kept for now to avoid surprises if the assumption
>
Em quinta-feira, 24 de maio de 2018 14:57:18 UTC-4, J. Kiszka escreveu:
> On 2018-05-24 16:50, Giovani Gracioli wrote:
> > Em quinta-feira, 24 de maio de 2018 10:44:10 UTC-4, J. Kiszka escreveu:
> >> On 2018-05-24 16:27, Giovani Gracioli wrote:
> >>>> On 2018-05
Em quinta-feira, 24 de maio de 2018 10:44:10 UTC-4, J. Kiszka escreveu:
> On 2018-05-24 16:27, Giovani Gracioli wrote:
> >> On 2018-05-24 15:59, Giovani Gracioli wrote:
> >>> Not sure about MMU on Erika.
> >>>
> >>> Yes, the fault is repor
> On 2018-05-24 15:59, Giovani Gracioli wrote:
> > Not sure about MMU on Erika.
> >
> > Yes, the fault is reported as well. This address is just another memory.
> > 0xA00.. is the BRAM and 0x500.. is the DRAM. Both have the same faulty
> > behavior when the si
Not sure about MMU on Erika.
Yes, the fault is reported as well. This address is just another memory.
0xA00.. is the BRAM and 0x500.. is the DRAM. Both have the same faulty behavior
when the size is 2MB.
> > Hi,
> >
> > The configs are attached. I am running Erika on the non-root cell.
>
> Do
Hi,
The configs are attached. I am running Erika on the non-root cell.
> > Don't know exactly why, but if I change the size for 1MB instead of 2MB, it
> > works.
> >
> > Is this because of this line in the mmu_cell.c?
> >
> > size = MIN(region_size, NUM_TEMPORARY_PAGES * PAGE_SIZE);
> >
> > T
Don't know exactly why, but if I change the size for 1MB instead of 2MB, it
works.
Is this because of this line in the mmu_cell.c?
size = MIN(region_size, NUM_TEMPORARY_PAGES * PAGE_SIZE);
Thus, is the maximum size of any memory region 1MB?
> Hi,
>
> I checked the array sizes and they are cor
Hi,
I checked the array sizes and they are correct. num_memory_regions uses the
ARRAY_SIZE macro:
.num_memory_regions = ARRAY_SIZE(config.mem_regions)
In Linux I can mmap and access the mapped region without errors.
Any other thought?
>
> Maybe the region was not properly registered. Did you
Hello,
I have a BRAM and DRAM blocks available on the FPGA side of the ZCU102 platform.
I would like to make them accessible for jailhouse cells. For instance, a BRAM
block is mapped to the 0xa000 address.
To do that, I inserted this address into the root and non-root cell
configurations a
I was right, the problem was related with the uio driver. The driver requires
the PCI_HOST_GENERIC to be enabled in the kernel. After enabling it (Bus
support -> PCI host controller drivers -> Generic PCI host controller),
jailhouse with vpci and interrupts works fine.
Best
Giovani
> Thank you
Thank you Jan. Yes, the issue was related to the UART clock as pointed out in
the another link.
To fix it, I added the following to the system-user.dtsi file:
/include/ "system-conf.dtsi"
/include/ "zynqmp-clk-ccf.dtsi"
/ {
clk100: clk100 {
compatible = "fixed-clock";
Hello,
I have a full Jailhouse setup (including ivshmem and interrupts) running on top
of the vanilla 4.14 kernel on the Xilinx Ultrascale+ platform. However, I need
to use some drivers only available on the Xilinx 4.14 kernel, so I am trying to
run Jailhouse on it.
I was able to compile and l
Thanks Jan.
By changing the bar_mask and having the two vpci devices mapped in different
pages, I was able to run it.
Can you please explain how the bar mask is used to define the address in which
the device is mapped to?
Giovani
> On 2018-05-04 16:59, Giovani Gracioli wrote:
> >
Thanks Jan.
Can you please explain the relation between the bar_mask bits and the interrupt
number?
The PCI interrupt for cell 1 is 140 and for cell 2 is 146. I tested both
individually and they work. However, when I have both cells running together,
the interrupts, as I said, are only sent to
, but it is
sent to cell 1, instead of cell 2.
Any advise on how to test this to find the error?
> On 2018-05-03 20:26, Giovani Gracioli wrote:
> > I noticed that if I set a higher bdf value (0x0 in one cell config and 0x10
> > in the another one) in the .pci_devices, I can se
I noticed that if I set a higher bdf value (0x0 in one cell config and 0x10 in
the another one) in the .pci_devices, I can see two different interrupts mapped
in Linux:
38: 2 0 GICv2 136 Edge uio_ivshmem
39: 5 0 GICv2 138 Edge uio_ivshmem
#
Hello,
I have configured ivshmem interrupts between the root-cell (Linux) and another
bare-metal cell on the ultrascale+ (arm64) platform.
What I would like to have now is another bare-metal cell, and then interrupts
among:
Linux <-> bare metal cell 1
Linux <-> bare metal cell 2
The idea is t
lt;< (142 - 128))
},
},
},
I attached here both configurations for those that want to use ivhsmem
interrupts in arm64. I would be happy to help to incorporate this working demo
into the master branch.
Giovani
> On 2018-04-17 15:17, Giovani Gracioli wrote:
> > It is not complet
I realized that I had forgot .num_irqchips = ARRAY_SIZE(config.irqchips) in the
non-root cell config.
After adding it to the non-root cell config and created the cell, I got the
following:
irqchip_set_pending(), local_injection = 0, sender (current cpu) = 3
irqchip_set_pending()-> memory_barrier
I realized that I had forgot .num_irqchips = ARRAY_SIZE(config.irqchips) in the
non-root cell config.
After adding it to the non-root cell config and created the cell, I got the
following:
irqchip_set_pending(), local_injection = 0, sender (current cpu) = 3
irqchip_set_pending()-> memory_barrie
I realized that I had forgot .num_irqchips = ARRAY_SIZE(config.irqchips) in the
non-root cell config.
When I added it to the cell config and created the cell, I got the following:
jailhouse cell create zynqmp-zcu102-gic-demo-i
irqchip_set_pending(), local_injection = 0, sender (current cpu) = 3
Thanks Jan.
So what I should do is to have a different IRQ for the root and non-root cells?
The root cell config has the following:
...
.vpci_irq_base = 136-32
...
.irqchips = {
/* GIC */ {
.address = 0xf901,
.pin_base = 32,
0xfc10 using mmap and then writes 1 to mapped_adress + 3.
> On 2018-04-16 23:53, Giovani Gracioli wrote:
> > I instrumented the code with several prints.
> >
> > When I start the bare-metal cell, I can see that an interrupt from CPU 3 is
> > issued and handled by C
ip_set_pending() -> just return after irqchip.inject_irq, cpu_data->cpu_id
= 0
Seems that the connection between Linux (root-cell) and the bare-metal one is
not correct, but the other way around is fine. Why is that?
> On 2018-04-16 20:35, Giovani Gracioli wrote:
> > I added .vpci
I added .vpci_irq_base = 136-32 to the bare-metal cell config (.cell) and now I
can see the interrupts generated by uio_send through the output of cat
/proc/interrupts:
CPU0 CPU1 CPU2
38: 38 0 0 GICv2 136 Edge uio_ivshmem,
uio_ivshmem
p-zcu102-gic-demo-ivshmem.cell
> > Created cell "gic-demo-ivshmem"
> > Page pool usage after cell creation: mem 56/995, remap 69/131072
> >
> > It seems that pci_cell_init() is not being called for the non-root cell.
> >
> > > Hi,
> > > a
"
> Page pool usage after cell creation: mem 56/995, remap 69/131072
>
> It seems that pci_cell_init() is not being called for the non-root cell.
>
> > Hi,
> > at a first look the configuration looks ok for me.
> >
> > Il giorno giovedì 12 aprile 2018 19:49:09
eing called for the non-root cell.
> Hi,
> at a first look the configuration looks ok for me.
>
> Il giorno giovedì 12 aprile 2018 19:49:09 UTC+2, Giovani Gracioli ha scritto:
> > Hello,
> >
> > Thank you for the answers.
> >
> > My comments are below.
&g
ys/class/uio/uio0/maps[0,1] is:
>
> cat /sys/class/uio/uio0/maps/map0/addr
> 0xfc10
> cat /sys/class/uio/uio0/maps/map0/offset
> 0x0
> cat /sys/class/uio/uio0/maps/map0/size
> 0x00001000
> cat /sys/class/uio/uio0/maps/map0/name
> reg
> >
> > 2018-04-12 8:01 GMT+02:00 Jan Kiszka :
> > On 2018-04-11 19:40, Giovani Gracioli wrote:
> >
> > > Here is the output of the unhandled data read:
> >
> > >
> >
> > > Unhandled data read at 0xfc10(2)
> >
&
; pci_find_device().
>
> If a decrease the while value test in the pci_find_device() function (bdf <
> 0x1), it does not find any PCI device (obviously) and there is no error.
>
> start_bdf is initially defined as 0xfc00, as configured in the root cell
> (.pc
000).
Any suggestion?
Giovani
> On 2018-04-10 16:39, Giovani Gracioli wrote:
> > Updating:
> >
> > I added
> >
> > .num_msix_vectors = 1,
> > .iommu = 1,
> >
> > to the root cell .pci_devices config, wrote a simple linux program to writ
ilhouse
> >
> > Here is the bit that finds the region
> > https://github.com/henning-schild-work/ivshmem-guest-code/blob/jailhouse/kernel_module/uio/uio_ivshmem.c#L96
> >
> > Also see:
> > https://github.com/henning-schild-work/ivshmem-guest-code/blob/
Thanks. I will use the ivshmem devices structure then.
> On 2018-04-09 18:51, Giovani Gracioli wrote:
> > Hello,
> >
> > I would like to send an IPI from the root cell (Linux) to an inmate cell on
> > arm64. I know Jailhouse isolates the physical cores and would no
e
>
> And you should not use JAILHOUSE_SHMEM_PROTO_VETH because you are not
> running a network-device on top of your shmem. Use _UNDEFINED or
> _CUSTOM instead.
>
> Henning
>
> Am Tue, 3 Apr 2018 10:47:31 -0700
> schrieb Giovani Gracioli <>:
>
> > Ju
Hello,
I would like to send an IPI from the root cell (Linux) to an inmate cell on
arm64. I know Jailhouse isolates the physical cores and would not allow to send
an IPI to a CPU that does not belong to the cell. However, I would like to test
that anyway.
I have a kernel module (Linux running
Just another info, after enabling the root cell, I can see the virtual pci
devices with lspci -v:
00:00.0 Unassigned class [ff01]: Red Hat, Inc Inter-VM shared memory
Subsystem: Red Hat, Inc Inter-VM shared memory
Flags: fast devsel
Memory at fc10 (64-bit, non-prefetch
Hello,
I would like to share buffers among cells on arm64 (Xilinx ultrascale+). The
documentation suggests the use of the ivshmem.
In order to use ivshmem, I changed the root cell config as follows (it is based
on the zynqmp-zcu102.c original file):
- In the .mem_regions:
/* IVSHMEM shared me
4-linux-gnu-gcc (Linaro GCC Snapshot 6.2-2016.11) 6.2.1 20161114
> Copyright (C) 2016 Free Software Foundation, Inc.
> This is free software; see the source for copying conditions. There is NO
> warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
>
> > On
s free software; see the source for copying conditions. There is NO
warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
> On 2017-12-12 16:20, Giovani Gracioli wrote:
> > Hello,
> >
> > I am trying to run the Jailhouse gic-demo on the Xilinx ZCU102 de
:18, Giovani Gracioli wrote:
> > After I rebooted, the error is back.
> >
>
> Then check what is behind 0x90003fe0 (/proc/iomem) and possibly add some
> permission to the root cell config. It might be a device we didn't use,
> thus didn't cover in the upstream conf
After I rebooted, the error is back.
> On 2017-12-12 18:55, Giovani Gracioli wrote:
> > Thanks Jan.
> >
> > Recompiled with kernel 4.15.4 (the last stable from mainline) and the error
> > disappeared.
> >
> > However, I am not able to see the
Thanks Jan.
Recompiled with kernel 4.15.4 (the last stable from mainline) and the error
disappeared.
However, I am not able to see the gic-demo output. I am connected in the
terminal /dev/ttyUSB0 (ttyPS0). There are four ttyUSB[0-3] mounted.
Where should gic-demo be printing to?
Giovani
--
Em terça-feira, 12 de dezembro de 2017 10:20:09 UTC-5, Giovani Gracioli
escreveu:
> Hello,
>
> I am trying to run the Jailhouse gic-demo on the Xilinx ZCU102 dev board.
> However, when I start the demo, I got an unhandled trap. Here are my steps:
>
> 1) modprobe jailhouse
Hello,
I am trying to run the Jailhouse gic-demo on the Xilinx ZCU102 dev board.
However, when I start the demo, I got an unhandled trap. Here are my steps:
1) modprobe jailhouse
syslog output:
Dec 11 18:39:54 linaro-gnome kernel: [ 25.666781] jailhouse: loading
out-of-tree module taints ke
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