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Hi all,
I'm trying to clear something up that's been bothering me for some time and
that is the MPC1/MPC2/MPC3E actual bandwidth specs. I know from various
sources that the MPC1 has a single Trio chipset, MPC2 has two Trio chipsets,
and the MPC3E has a single enhanced Trio chipset.
The
On 5/30/14, 10:32 AM, Eric Van Tol wrote:
Hi all, I'm trying to clear something up that's been bothering me for
some time and that is the MPC1/MPC2/MPC3E actual bandwidth specs. I
know from various sources that the MPC1 has a single Trio chipset,
MPC2 has two Trio chipsets, and the MPC3E has
On (2014-05-30 11:54 -0700), joel jaeggli wrote:
the bandwidth is symmetric... the forwarding lookup is only done on the
ingress linecard.
(Memory) bandwidth is unidir, single Trio has maybe 70Gbps of memory bandwidth
(it depends on cell alignment, it can be 80Gbps and in artificial scenario
I have the most familiarity with the 16x10GE cards which use 4 Trio chips,
but are similar to the other MPC2 cards.
Each of those Trio chips has 70G of bandwidth shared between the ingress
ports and the fabric like you mentioned. Traffic going in/out of the same
PFE doesn't count against the
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