https://bugs.kde.org/show_bug.cgi?id=377966
Joseph changed:
What|Removed |Added
CC||jga...@hmc.edu
--- Comment #7 from Joseph ---
Warning
https://bugs.kde.org/show_bug.cgi?id=377966
--- Comment #6 from Antonio Ospite ---
BTW in my case the unhandled instruction was in an optimized version of memset,
I was able to revert to a non-optimized version and progress further in my
debugging session.
I am mentioning this because looking up
https://bugs.kde.org/show_bug.cgi?id=377966
Antonio Ospite changed:
What|Removed |Added
Assignee|jsew...@acm.org |assad.has...@linaro.org
Platform|Fed
https://bugs.kde.org/show_bug.cgi?id=377966
Mark Wielaard changed:
What|Removed |Added
CC||m...@klomp.org
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https://bugs.kde.org/show_bug.cgi?id=377966
Antonio Ospite changed:
What|Removed |Added
CC||a...@ao2.it
Version|3.12.0
https://bugs.kde.org/show_bug.cgi?id=377966
--- Comment #4 from Peter Maydell ---
Good point -- there's no inherent reason why valgrind would need to use the
same cache line size that the host is using for DC ZVA. You can just pick an
arbitrary value as long as you're consistent with the value of
https://bugs.kde.org/show_bug.cgi?id=377966
--- Comment #3 from John Reiser ---
(In reply to Julian Seward from comment #1)
> The main difficulty is to know how big the cache line is.
The value (and validity) is reported by the instruction "mrs reg, dczid_el0".
So valgrind could add that to its
https://bugs.kde.org/show_bug.cgi?id=377966
Peter Maydell changed:
What|Removed |Added
CC||peter.mayd...@linaro.org
--- Comment #2 from Pe
https://bugs.kde.org/show_bug.cgi?id=377966
--- Comment #1 from Julian Seward ---
(In reply to John Reiser from comment #0)
> instruction; it [allocates and] clears the cache line whose address
> corresponds to the contents of register x5.
Yes, ppc has something similar iirc (dcbz). The main di
https://bugs.kde.org/show_bug.cgi?id=377966
John Reiser changed:
What|Removed |Added
Summary|disInstr(arm64): unhandled |disInstr(arm64): unhandled
|ins
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