>1. use early_param to get the physical start address and size of
test_region, or you can just ignore this step and hard code to 510M and 2M
for test purpose only.
>2. use ioremap_nocache() to map this region to a virtual region. note that
this funtion may fail if you are asking a very large vitua
>1. use early_param to get the physical start address and size of
test_region, or you can just ignore this step and hard code to 510M and 2M
for test purpose only.
>2. use ioremap_nocache() to map this region to a virtual region. note that
this funtion may fail if you are asking a very large vitua
On Wed, Feb 27, 2013 at 10:19 PM, Mylene Josserand
wrote:
> Just to update you that I have found my problem !
>
> In my config file, I did not notice that my own board and an other imx27
> board was enabled ! So the gpios configured was the one from this board
> and not mine's (thanks debugfs !).
On Wed, 27 Feb 2013 15:38:00 +0530, sandeep kumar said:
> In development phase of the board, we are trying to measure RAM performance
> gain while changing type of the RAM.
> The standard benchmark tools are giving us the Cache performance only. So
> we want to try some method to measure RAM perfo
Just to update you that I have found my problem !
In my config file, I did not notice that my own board and an other imx27
board was enabled ! So the gpios configured was the one from this board
and not mine's (thanks debugfs !). That is why it did not act like I wanted.
Otherwise, the gpios ar
> From: bu...@live.cn
> To: coolsandyfor...@gmail.com; kernelnewbies@kernelnewbies.org
> Subject: RE: How to measure the RAM read/write performance
> Date: Wed, 27 Feb 2013 22:33:15 +0800
> CC: dhyla...@gmail.com
>
>
> > From
> From: coolsandyfor...@gmail.com
> Date: Tue, 26 Feb 2013 17:01:54 +0530
> Subject: How to measure the RAM read/write performance
> To: kernelnewbies@kernelnewbies.org
> CC: dhyla...@gmail.com
>
> Hi All
> In performance benchmark tools, When we profile read
On Wed, Feb 27, 2013 at 6:16 PM, sandeep kumar
wrote:
>>Try below points:
>>1. I am not sure about snapdragon(is it Qualcomm?) but try
>>CONFIG_CPU_DCACHE_DISABLE.
> I did that already, device is not booting. In our architecture cache is
> tightly coupled with CPU.
Should be discussed with Qualcom
>Try below points:
>1. I am not sure about snapdragon(is it Qualcomm?) but try
>CONFIG_CPU_DCACHE_DISABLE.
I did that already, device is not booting. In our architecture cache is
tightly coupled with CPU.
>2. You are better off programming some DMA master to do large (and
>uncached) reads/writes t
On Tue, Feb 26, 2013 at 5:01 PM, sandeep kumar
wrote:
> Hi All
> In performance benchmark tools, When we profile read/write timings mostly,
> those read/writes are done to cache only.
>
> I want to measure my DDR(RAM chip) performance.
> So i want to make sure, every read/write should happen to DD
2013/2/27 sandeep kumar
> >"volatile" only say to the compiler to not put the variable in a register.
> >Could i ask why does you want to mesure the speed of the RAM ? Is it to
> study the NUMA behavior of the machine?
>
> In development phase of the board, we are trying to measure RAM
> performa
Hi everyone !
I am currently updating the kernel of my company and I have some
problems about gpios so I am asking you some help ! :)
I think I am in the good mailist because it is the first time I update a
kernel and a board configuration ! :D
The previous kernel used was 2.6.31.14 and I am t
>"volatile" only say to the compiler to not put the variable in a register.
>Could i ask why does you want to mesure the speed of the RAM ? Is it to
study the NUMA behavior of the machine?
In development phase of the board, we are trying to measure RAM performance
gain while changing type of the R
2013/2/27 sandeep kumar
> >>I am not sure but what if you make the variable as a volatile?
> Hey i tried. But still is showing the same time for int & volatile int.
>
>
"volatile" only say to the compiler to not put the variable in a register.
Could i ask why does you want to mesure the speed of
>let' see
>what if you do read and write pattern, in certain order so that it
>will be invalidated by the L1/L2/L3 cache everytime?
And how do you suggest we do that?? That is infact my question..
On Tue, Feb 26, 2013 at 9:05 PM, Mulyadi Santosa
wrote:
> On Tue, Feb 26, 2013 at 6:31 PM, s
>>I am not sure but what if you make the variable as a volatile?
Hey i tried. But still is showing the same time for int & volatile int.
Thanks
Sandeep
On Tue, Feb 26, 2013 at 6:50 PM, ankur dwivedi wrote:
> I am not sure but what if you make the variable as a volatile?
>
> On Tue, Feb 26, 201
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