Hi,
I can reproduct this problem even when I build from source. To do that I
just activate KICAD_SCRIPTING_WXPYTHON during compilation and I face the
same issue.
I imagine that the issue is somewhere on links options ...
I found 2 workarrounds:
- Disable this option
- force loading of python2.7
You mean it not build at all ?
This warning look to be logical since the value is not used but it should
not break the building process
You can try to replace
void* handle = dlopen(libpython2.7.so, RTLD_LAZY | RTLD_GLOBAL);
by
dlopen(libpython2.7.so, RTLD_LAZY | RTLD_GLOBAL);
On 04/04/2014 01:02 AM, Jean-Samuel Reynaud wrote:
=== modified file 'common/single_top.cpp'
--- common/single_top.cpp 2014-03-21 16:59:19 +
+++ common/single_top.cpp 2014-03-28 22:01:08 +
@@ -221,6 +221,8 @@
{
bool OnInit() // overload wxApp virtual
{
Both look great, but I prefer option 1.
What if the project-specific libraries were also accessible from there? I
know it's not in the initial requirements; I'm just throwing in the idea.
On Fri, Apr 4, 2014 at 10:41 AM, Dick Hollenbeck d...@softplc.com wrote:
Thanks Jean-Samuel, very very
On 04/04/2014 10:14 AM, Carl Poirier wrote:
Both look great, but I prefer option 1.
What if the project-specific libraries were also accessible from there?
Accessible in what way? Please elaborate in detail.
I know it's not in
the initial requirements; I'm just throwing in the idea.
On Fri, Apr 04, 2014 at 08:37:05AM -0500, Dick Hollenbeck wrote:
Is there something wrong with my BOARD?
If so, what?
AFAIK they appeared with the CERN router merge... they said it was
something like unsupported pad configurations (like a soldermask only
pad and stuff).
Seems harmless but I
Le 04/04/2014 15:04, Dick Hollenbeck a écrit :
I'm sure you are not submitting this for a potential commit, right?
Clearly the objectif of this patch is NOT to be commit.
Because:
1) The comment is below the line of text that it refers to.
Yes it's a paste an copy from a solution I found on
On 04/04/2014 11:10 AM, Jean-Samuel Reynaud wrote:
Le 04/04/2014 15:04, Dick Hollenbeck a écrit :
I'm sure you are not submitting this for a potential commit, right?
Clearly the objectif of this patch is NOT to be commit.
Because:
1) The comment is below the line of text that it refers to.
On 04/04/2014 11:08 AM, Lorenzo Marcantonio wrote:
On Fri, Apr 04, 2014 at 08:37:05AM -0500, Dick Hollenbeck wrote:
Is there something wrong with my BOARD?
If so, what?
AFAIK they appeared with the CERN router merge... they said it was
something like unsupported pad configurations (like a
I have try to find a solution by trace the library loading:
LD_DEBUG=all pcbnew
But the issue look to be due to a compilation option on some ubuntu
libs. Anyway I'm NOT sure of that...
This is the right path to an understanding. It's just that full source level
debugging is
needed to see
I am in the process of migrating my personal footprint an schematic part
libraries to
using A and C for pad/pin names.
Away from 1 and 2.
Other than the fact that I now have the burden of maintaining every footprint
and
schematic part object myself relating to all things diode, from now to
On 04/04/2014 06:08 PM, Lorenzo Marcantonio wrote:
On Fri, Apr 04, 2014 at 08:37:05AM -0500, Dick Hollenbeck wrote:
Is there something wrong with my BOARD?
If so, what?
AFAIK they appeared with the CERN router merge... they said it was
something like unsupported pad configurations (like a
Ladies and gentlemen,
As it was recently promised, we have fixed many bugs and added some new
features to the GAL canvas in pcbnew (branch
lp:~cern-kicad/kicad/drawing_tool).
Main changes include:
- edit points for dimensions
- zones got a new edit mode (I call it 'keep side slope', you can
On 04/04/2014 12:21 PM, Maciej Sumiński wrote:
Ladies and gentlemen,
As it was recently promised, we have fixed many bugs and added some new
features to the GAL canvas in pcbnew (branch
lp:~cern-kicad/kicad/drawing_tool).
Main changes include:
- edit points for dimensions
- zones got
Le 04/04/2014 19:20, Maciej Sumiński a écrit :
On 04/04/2014 06:08 PM, Lorenzo Marcantonio wrote:
On Fri, Apr 04, 2014 at 08:37:05AM -0500, Dick Hollenbeck wrote:
Is there something wrong with my BOARD?
If so, what?
AFAIK they appeared with the CERN router merge... they said it was
2014-04-04 19:24 GMT+02:00 Dick Hollenbeck d...@softplc.com:
I am in the process of migrating my personal footprint an schematic part
libraries to
using A and C for pad/pin names.
Away from 1 and 2.
Other than the fact that I now have the burden of maintaining every footprint
and
Le 04/04/2014 20:02, Nick Østergaard a écrit :
I might very well be a good idea -- same goes for transistors. But
what would you do with a BAT54S? This is a three pin package with two
diodes in series with a pin in between. One could still stick with
numbers for all those doubtfull packages,
On 04/04/2014 01:02 PM, Nick Østergaard wrote:
2014-04-04 19:24 GMT+02:00 Dick Hollenbeck d...@softplc.com:
I am in the process of migrating my personal footprint an schematic part
libraries to
using A and C for pad/pin names.
Away from 1 and 2.
Other than the fact that I now have the
I am thinking this is a very old debug message, which can be dropped.
Thanks.
Done.
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I think this is a very good idea. I will add this to our upcoming KiCad
library convention. Many transistors use letters already.
As for capacitors, why not also using C and A for cathode and anode?
On Fri, Apr 4, 2014 at 2:24 PM, jp charras jp.char...@wanadoo.fr wrote:
Le 04/04/2014 20:02,
-BEGIN PGP SIGNED MESSAGE-
Hash: SHA1
On 04/04/2014 10:45 PM, Carl Poirier wrote:
I think this is a very good idea. I will add this to our upcoming
KiCad library convention. Many transistors use letters already.
I do not agree for footprints, because - at least if I understand the
The double diodes in SOT23 packages are really confusing since there are
several configurations possible,
and they are all existing.
Pin
1 2 3 --- Pin 1
A1, C1A2, C2 Pin 2SOT23
C1, A1C2, A2
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