On 13/06/14 21:23, Nick Østergaard wrote:
> I like the 3D view very much, even the old simple one is great for
> verifying tracks. I often find things I want to change when looking at
> the 3D view of just the traces and silk.
I agree, I think it's having an alaternative perspective. A bit like
g
Den 13/06/2014 21.43 skrev "Lorenzo Marcantonio" :
>
> On Fri, Jun 13, 2014 at 08:33:02PM +0100, John Beard wrote:
> > OK, I won't worry too much about it and get one with making more
> > footprints! Are there any more things you'd like to see changed? No
> > matter how tiny!
>
> These are already
On 13/06/14 20:44, Lorenzo Marcantonio wrote:
> On Fri, Jun 13, 2014 at 08:33:02PM +0100, John Beard wrote:
>> OK, I won't worry too much about it and get one with making more
>> footprints! Are there any more things you'd like to see changed? No
>> matter how tiny!
>
> These are already *way* nic
On Fri, Jun 13, 2014 at 08:33:02PM +0100, John Beard wrote:
> OK, I won't worry too much about it and get one with making more
> footprints! Are there any more things you'd like to see changed? No
> matter how tiny!
These are already *way* nicer than the ones I use at the moment:D
You know, usual
On 13/06/14 19:36, Lorenzo Marcantonio wrote:
> On Fri, Jun 13, 2014 at 06:46:37PM +0100, John Beard wrote:
>> The silk screen is put so it can be seen after soldering. The ASCII art
>> arrow is an assembly layer feature, modelled after the IPC standard.
>
> Sorry my fault. I was thinking was a fa
On Fri, Jun 13, 2014 at 06:46:37PM +0100, John Beard wrote:
> The silk screen is put so it can be seen after soldering. The ASCII art
> arrow is an assembly layer feature, modelled after the IPC standard.
Sorry my fault. I was thinking was a fancy silk. IPC assemblies are
simply notched rectangles
On Sun, Jun 08, 2014 at 11:35:26AM -0400, Jean-Paul Louis wrote:
> When the board is fully assembled, the outline is meaningless, only the
> RefDes keep its value.
Pin 1/polarization marks keep their value for inspection.
> And there is no difference in purpose between Through Hole and Surface
On Mon, Jun 02, 2014 at 10:32:18AM -0400, Jean-Paul Louis wrote:
> Guys,
>
> I am reading all this thread, and I am amazed that people suggest a silk
> shape that will HAVE TO BE REMOVED by the PCB fabricator.
The industry took a long time to discover this, too :D
And it isn't a full standard ye
Guys,
I am reading all this thread, and I am amazed that people suggest a silk shape
that will HAVE TO BE REMOVED by the PCB fabricator.
This is adding cost to a PCB without any value added.
The example shown by Lorenzo is a very good example. The yellow rectangle has
zero value AND an extra co
On Sun, Jun 01, 2014 at 10:42:33PM +0100, John Beard wrote:
> I have never registered erasure of silk over pads as a problem, no
> fabricator has ever complained or delivered over-printed pads. Has
> anyone seen this happen?
Neither have I. Simply because our fabricator erase everything in 0.2mm
o
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