*Hi friends, associates, partners* * *
*Kindly Share me the matching resumes to **riz...@javaji.com*** * * * * *Position: Senior Physical Design Engineer* *Duration: 5 months* *Location: Oregon* · Should be familiar with hierarchical and flat design methodologies, Knowledge of Perl/TCL is strongly preferred. · Successful track record of having worked on designs which went into production is a must. · Hands on knowledge in physical design flow of multi million gate designs including floorplanning, power routing, EM and IR drop analysis, Constraints development, Timing Closure including. Synthesis, pre-layout and post-layout Static Timing Analysis;Clock Tree Synthesis and Routing, Physical; verification including DRC, LVS, Noise, Antenna checks · implementation, Synopsys flow experience Synopsys IC Compiler, Hercules DRC.. *Thanks and Regards,* * Ashik Rizwan* *Javaji Solutions* *riz...@javaji.com* *Direct: 571-642-1123* *Fax: 703-880-7232* *www.javaji.com* -- You received this message because you are subscribed to the Google Groups "KNOW.IT" group. To post to this group, send email to know_it...@googlegroups.com. To unsubscribe from this group, send email to know_it_az+unsubscr...@googlegroups.com. For more options, visit this group at http://groups.google.com/group/know_it_az?hl=en.
