Avi Kivity wrote:
Michael Malone wrote:
Hi everyone,
I've written a couple of questions regarding the serial device in
KVM. After slightly more investigation I think I have found what's
going awry. Correct me if I'm wrong, but I believe that KVM
generates an interrupt for every single char
Bugs item #2063072, was opened at 2008-08-20 17:29
Message generated for change (Comment added) made by freedombi
You can respond by visiting:
https://sourceforge.net/tracker/?func=detail&atid=893831&aid=2063072&group_id=180599
Please note that this message will contain a full copy of the comment
As discussed in
http://lists.gnu.org/archive/html/qemu-devel/2008-08/msg00667.html,
current pxe boot is broken for some use cases. The problem
goes away if we reduce the number of allowed bits in the address space
to 32 (which has the side effect of reducing guest max mem size to 4Gb).
After diggi
Bugs item #2087432, was opened at 2008-09-01 21:56
Message generated for change (Tracker Item Submitted) made by Item Submitter
You can respond by visiting:
https://sourceforge.net/tracker/?func=detail&atid=893831&aid=2087432&group_id=180599
Please note that this message will contain a full copy
Avi Kivity wrote:
If the kernel was built, installed, and is now running,
it's not. change control, downtime windows and such like nonsense prevent me from doing things that way. The target systems don't
have any development tools installed and the build system will never run the kernel being
The remote tlb flush in kvm_mmu_page_unlink_children() is not necessary because
this function is only called in kvm_mmu_zap_page() which does the flush itself
afterwards.
Signed-off-by: Joerg Roedel <[EMAIL PROTECTED]>
---
arch/x86/kvm/mmu.c |1 -
1 files changed, 0 insertions(+), 1 deletions
Am 01.09.2008 um 18:17 schrieb Avi Kivity <[EMAIL PROTECTED]>:
Alexander Graf wrote:
We can't change struct kvm_sregs, since the structure size is
encoded in the ioctl number. We need a new struct and new
ioctls. The same was done for mpstate, for example.
Urks - doesn't sounds fast t
* Zhao, Yu <[EMAIL PROTECTED]>:
> Support SR-IOV capability. By default, this feature is not enabled and the
> SR-IOV device behaves as traditional PCI device. After it's enabled, each
> Virtual Function's PCI configuration space can be accessed using its own Bus,
> Device and Function Number (R
Peter Zijlstra wrote:
Avi, the below fixes it for me..
For me too. Thanks!
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Alexander Graf wrote:
We can't change struct kvm_sregs, since the structure size is encoded
in the ioctl number. We need a new struct and new ioctls. The same
was done for mpstate, for example.
Urks - doesn't sounds fast to me.
It's only for save/restore, not in any fast path.
There
* Zhao, Yu <[EMAIL PROTECTED]>:
> Some basic changes to allocation bus range, MMIO resource for SR-IOV device.
This following comment is a bit confusing:
> And add new sysfs entry to hotplug core to pass parameter to a
> slot, which will be used by SR-IOV code.
I was reading this patch, expecting
On Sep 1, 2008, at 6:05 PM, Avi Kivity wrote:
Alexander Graf wrote:
It's not visible in the patches I sent, but I did use the hflags
for a VMLOAD+VMRUN+VMSAVE aggregation hack. It's still somewhat
flacky wrt save/restore though, so I didn't send it. Hflags might
be useful nevertheless tho
Alexander Graf wrote:
It's not visible in the patches I sent, but I did use the hflags for
a VMLOAD+VMRUN+VMSAVE aggregation hack. It's still somewhat flacky
wrt save/restore though, so I didn't send it. Hflags might be useful
nevertheless though.
You mean code patching?
Yes.
That's alway
Fix coding style in test_eflags_insn() in real mode test harness.
Signed-off-by: Mohammed Gamal <[EMAIL PROTECTED]>
---
user/test/x86/realmode.c | 10 +-
1 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/user/test/x86/realmode.c b/user/test/x86/realmode.c
index d760a26..462
> > +config PCI_ARI
> > + bool "PCI ARI support"
> > + depends on PCI
> > + default n
> > + help
> > +This enables PCI Alternative Routing-ID Interpretation.
>
> This Kconfig help text is a little weak. Why not include the text
> you've already written here:
>
> Support Al
* Zhao, Yu <[EMAIL PROTECTED]>:
> +1. Overview
> +
> +1.1 What is SR-IOV
> +
> +Single Root I/O Virtualization (SR-IOV) is a PCI Express Extended
> +capability which makes one physical device appear as multiple virtual
> +devices. The physical device is referred to as Physical Function while
> +the
On Sep 1, 2008, at 4:25 PM, Avi Kivity wrote:
Alexander Graf wrote:
+
+u32 hflags;
};
bool gif : 1;
(or even
bool gif;)?
It's not visible in the patches I sent, but I did use the hflags
for a VMLOAD+VMRUN+VMSAVE aggregation hack. It's still somewhat
flacky wrt save/restore thoug
* Zhao, Yu <[EMAIL PROTECTED]>:
> Support SR-IOV capability. By default, this feature is not enabled and the
> SR-IOV device behaves as traditional PCI device. After it's enabled, each
> Virtual Function's PCI configuration space can be accessed using its own Bus,
> Device and Function Number (R
* Zhao, Yu <[EMAIL PROTECTED]>:
> Support Alternative Routing-ID Interpretation (ARI), which increases the
> number of functions that can be supported by a PCIe endpoint. ARI is required
> by SR-IOV.
>
> PCI-SIG ARI specification can be found at
> http://www.pcisig.com/specifications/pciexpress
/kernel subdir layout changed a while ago. Update gitignore to reflect
this.
Signed-off-by: Jan Kiszka <[EMAIL PROTECTED]>
---
diff --git a/.gitignore b/.gitignore
index 7422760..bb35cca 100644
--- a/.gitignore
+++ b/.gitignore
@@ -15,19 +15,6 @@ qemu/qemu-img
qemu/qemu-nbd
*.ko
*.mod.c
-kernel
Avi, the below fixes it for me..
---
Subject: sched_clock: fix NOHZ interaction
From: Peter Zijlstra <[EMAIL PROTECTED]>
Date: Mon Sep 01 16:44:23 CEST 2008
If HLT stops the TSC, we'll fail to account idle time, thereby inflating the
actual process times. Fix this by re-calibrating the clock aga
Alexander Graf wrote:
On Sep 1, 2008, at 4:22 PM, Avi Kivity wrote:
Alexander Graf wrote:
This is completely implementation specific. So for now this is 100%
AMD only code.
Also I don't really like Intel's design for VMX and while making
nested VMX work might not be _that_ hard, getting it
On Sep 1, 2008, at 4:27 PM, Avi Kivity wrote:
Alexander Graf wrote:
On Sep 1, 2008, at 3:27 PM, Avi Kivity wrote:
Alexander Graf wrote:
This implements the VMLOAD and VMSAVE instructions, that usually
surround
the VMRUN instructions. Both instructions load / restore the same
elements,
On Sep 1, 2008, at 4:22 PM, Avi Kivity wrote:
Alexander Graf wrote:
This is completely implementation specific. So for now this is 100%
AMD only code.
Also I don't really like Intel's design for VMX and while making
nested VMX work might not be _that_ hard, getting it fast would
probabl
On Mon, 2008-09-01 at 15:37 +0300, Avi Kivity wrote:
> Why? A local application will have exactly the same problems with a
> broken dns server on localhost, as a virtual machine with that address
> forwarded. And if the the dns server is later fixed, both the local
> application and the guest
Alexander Graf wrote:
On Sep 1, 2008, at 3:27 PM, Avi Kivity wrote:
Alexander Graf wrote:
This implements the VMLOAD and VMSAVE instructions, that usually
surround
the VMRUN instructions. Both instructions load / restore the same
elements,
so we only need to implement them once.
+static in
Alexander Graf wrote:
On Sep 1, 2008, at 3:15 PM, Avi Kivity wrote:
Alexander Graf wrote:
Implement the hsave MSR, that gives the VCPU a GPA to save the
old guest state in.
There's a list of msrs exported to userspace somewhere; adding this
will automatically add save/restore/migrate supp
Alexander Graf wrote:
+
+u32 hflags;
};
bool gif : 1;
(or even
bool gif;)?
It's not visible in the patches I sent, but I did use the hflags for a
VMLOAD+VMRUN+VMSAVE aggregation hack. It's still somewhat flacky wrt
save/restore though, so I didn't send it. Hflags might be useful
nev
Alexander Graf wrote:
This is completely implementation specific. So for now this is 100%
AMD only code.
Also I don't really like Intel's design for VMX and while making
nested VMX work might not be _that_ hard, getting it fast would
probably require a lot of work and hacks.
I've thought of
On Sep 1, 2008, at 3:41 PM, Daniel P. Berrange wrote:
On Mon, Sep 01, 2008 at 01:57:52PM +0200, Alexander Graf wrote:
The current generation of virtualization extensions only supports
one VM layer.
While we can't change that, it is pretty easy to emulate the CPU's
behavior
and implement th
On Sep 1, 2008, at 3:27 PM, Avi Kivity wrote:
Alexander Graf wrote:
This implements the VMLOAD and VMSAVE instructions, that usually
surround
the VMRUN instructions. Both instructions load / restore the same
elements,
so we only need to implement them once.
+static int nested_svm_vmloadsa
On Sep 1, 2008, at 3:15 PM, Avi Kivity wrote:
Alexander Graf wrote:
Implement the hsave MSR, that gives the VCPU a GPA to save the
old guest state in.
There's a list of msrs exported to userspace somewhere; adding this
will automatically add save/restore/migrate support for hsave.
Sound
On Sep 1, 2008, at 3:11 PM, Avi Kivity wrote:
Alexander Graf wrote:
This patch implements the GIF flag and the clgi and stgi
instructions that
set this flag. Only if the flag is set (default), interrupts can be
received by
the CPU.
To keep the information about that somewhere, this patch
Alexander Graf wrote:
Usually the qemu-kvm-bridge removes the SVM capability flag. Since KVM now
supports nested SVM, this is no longer necessary.
Signed-off-by: Alexander Graf <[EMAIL PROTECTED]>
---
qemu/qemu-kvm-x86.c |3 ---
1 files changed, 0 insertions(+), 3 deletions(-)
diff --git a
Alexander Graf wrote:
This adds the #VMEXIT intercept, so we return to the level 1 guest
when something happens in the level 2 guest that should return to
the level 1 guest.
@@ -223,6 +228,21 @@ static void svm_queue_exception(struct kvm_vcpu *vcpu,
unsigned nr,
{
struct vcpu_svm *svm
Alexander Graf wrote:
This patch implements VMRUN. VMRUN enters a virtual CPU and runs that
in the same context as the normal guest CPU would run.
So basically it is implemented the same way, a normal CPU would do it.
We also prepare all intercepts that get OR'ed with the original
intercepts, as
On Mon, Sep 01, 2008 at 01:57:52PM +0200, Alexander Graf wrote:
> The current generation of virtualization extensions only supports one VM
> layer.
> While we can't change that, it is pretty easy to emulate the CPU's behavior
> and implement the virtualization opcodes ourselves.
>
> This patchset
Alexander Graf wrote:
This implements the VMLOAD and VMSAVE instructions, that usually surround
the VMRUN instructions. Both instructions load / restore the same elements,
so we only need to implement them once.
+static int nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb)
+
Alexander Graf wrote:
@@ -1360,6 +1361,9 @@ static int svm_get_msr(struct kvm_vcpu *vcpu, unsigned
ecx, u64 *data)
case MSR_IA32_LASTINTTOIP:
*data = svm->vmcb->save.last_excp_to;
break;
+ case MSR_VM_HSAVE_PA:
+ *data = svm->nested_hsa
Alexander Graf wrote:
Implement the hsave MSR, that gives the VCPU a GPA to save the
old guest state in.
There's a list of msrs exported to userspace somewhere; adding this will
automatically add save/restore/migrate support for hsave.
--
error compiling committee.c: too many arguments to
Alexander Graf wrote:
Normally setting the SVME bit in EFER is not allowed, as we did
not support SVM. Not since we do, we should also allow enabling
SVM mode.
Signed-off-by: Alexander Graf <[EMAIL PROTECTED]>
---
arch/x86/kvm/svm.c |2 ++
1 files changed, 2 insertions(+), 0 deletions(-)
d
Alexander Graf wrote:
The current VINTR intercept setters don't look clean to me. To make
the code easier to read and enable the possibilty to trap on a VINTR
set, this uses a helper function to set the VINTR intercept.
+static void svm_set_vintr(struct vcpu_svm *svm, bool on)
+{
+ if (on)
Alexander Graf wrote:
This patch implements the GIF flag and the clgi and stgi instructions that
set this flag. Only if the flag is set (default), interrupts can be received by
the CPU.
To keep the information about that somewhere, this patch adds a new hidden
flags vector. that is used to store
On Fri, Aug 22, 2008 at 10:10:52AM +0300, Amit Shah wrote:
>
> The following two patches contain VT-d support for device assignment
> for KVM guests.
>
> The first patch contains the changes that are required to the generic
> VT-d code.
>
> The second patch contains the changes to KVM.
>
> I've
Hey.
I'm observing some network problems when using virtio and a tap if.
The trouble is a drop of network troughput from abot 90Mbit/s to about 90kbit/s,
after about 1.7 TB of transferred data.
Setup
Host:
- Fedora 8, nearly all updates
- Intel(R) Xeon(R) CPU X3210 @ 2.13GHz
- 8GB RAM
Cristi Magherusan wrote:
On Mon, 2008-09-01 at 14:14 +0300, Avi Kivity wrote:
Cristi Magherusan wrote:
Those who have installed a local DNS server may need that stuff, but we
can check every entries of resolv.conf and see if we can connect to
their DNS server, and use in our VM the firs
On Mon, 2008-09-01 at 14:14 +0300, Avi Kivity wrote:
> Cristi Magherusan wrote:
> > Those who have installed a local DNS server may need that stuff, but we
> > can check every entries of resolv.conf and see if we can connect to
> > their DNS server, and use in our VM the first one that could be rea
On Mon, Sep 01, 2008 at 01:57:52PM +0200, Alexander Graf wrote:
> The current generation of virtualization extensions only supports one VM
> layer.
> While we can't change that, it is pretty easy to emulate the CPU's behavior
> and implement the virtualization opcodes ourselves.
>
> This patchset
Alexander Graf wrote:
The current generation of virtualization extensions only supports one VM layer.
While we can't change that, it is pretty easy to emulate the CPU's behavior
and implement the virtualization opcodes ourselves.
This patchset does exactly this for SVM. Using this, a KVM can run
[EMAIL PROTECTED] wrote:
From: Sheng Yang <[EMAIL PROTECTED]>
EPT is 4 level by default in 32pae(48 bits), but the addr parameter
of kvm_shadow_walk->entry() only accept unsigned long as virtual
address, which is 32bit in 32pae. This result in SHADOW_PT_INDEX()
overflow when try to fetch level 4
Add the SVM capability to the external module compat header, so we can use it
when the kernel does not know about this define.
Signed-off-by: Alexander Graf <[EMAIL PROTECTED]>
---
kernel/x86/external-module-compat.h |4
1 files changed, 4 insertions(+), 0 deletions(-)
diff --git a/kern
This is the userspace part of the nested SVM series. It enables building
the nested SVM code as external module and passes through the SVM CPUID bit
to the VM.
Alexander Graf (2):
Add SVM CPUID feature define for backwards compatibility
Allow the SVM CPUID bit in a VM
kernel/x86/external-mod
Usually the qemu-kvm-bridge removes the SVM capability flag. Since KVM now
supports nested SVM, this is no longer necessary.
Signed-off-by: Alexander Graf <[EMAIL PROTECTED]>
---
qemu/qemu-kvm-x86.c |3 ---
1 files changed, 0 insertions(+), 3 deletions(-)
diff --git a/qemu/qemu-kvm-x86.c b/q
This patch implements VMRUN. VMRUN enters a virtual CPU and runs that
in the same context as the normal guest CPU would run.
So basically it is implemented the same way, a normal CPU would do it.
We also prepare all intercepts that get OR'ed with the original
intercepts, as we do not allow a level
This adds the #VMEXIT intercept, so we return to the level 1 guest
when something happens in the level 2 guest that should return to
the level 1 guest.
Signed-off-by: Alexander Graf <[EMAIL PROTECTED]>
---
arch/x86/kvm/svm.c | 305
1 files cha
These are helpers for the nested SVM implementation.
- nsvm_printk implements a debug printk variant
- nested_svm_do calls a handler that can accesses gpa-based memory
Signed-off-by: Alexander Graf <[EMAIL PROTECTED]>
---
arch/x86/kvm/svm.c | 76
This patch implements the GIF flag and the clgi and stgi instructions that
set this flag. Only if the flag is set (default), interrupts can be received by
the CPU.
To keep the information about that somewhere, this patch adds a new hidden
flags vector. that is used to store information that does n
This implements the VMLOAD and VMSAVE instructions, that usually surround
the VMRUN instructions. Both instructions load / restore the same elements,
so we only need to implement them once.
Signed-off-by: Alexander Graf <[EMAIL PROTECTED]>
---
arch/x86/kvm/svm.c | 69 +++
This patch adds the CPUID feature flag for SVM in the x86 Linux headers.
Signed-off-by: Alexander Graf <[EMAIL PROTECTED]>
---
include/asm-x86/cpufeature.h |1 +
1 files changed, 1 insertions(+), 0 deletions(-)
diff --git a/include/asm-x86/cpufeature.h b/include/asm-x86/cpufeature.h
index 76
The current VINTR intercept setters don't look clean to me. To make
the code easier to read and enable the possibilty to trap on a VINTR
set, this uses a helper function to set the VINTR intercept.
Signed-off-by: Alexander Graf <[EMAIL PROTECTED]>
---
arch/x86/kvm/svm.c | 19 ++-
Normally setting the SVME bit in EFER is not allowed, as we did
not support SVM. Not since we do, we should also allow enabling
SVM mode.
Signed-off-by: Alexander Graf <[EMAIL PROTECTED]>
---
arch/x86/kvm/svm.c |2 ++
1 files changed, 2 insertions(+), 0 deletions(-)
diff --git a/arch/x86/kvm
The current generation of virtualization extensions only supports one VM layer.
While we can't change that, it is pretty easy to emulate the CPU's behavior
and implement the virtualization opcodes ourselves.
This patchset does exactly this for SVM. Using this, a KVM can run within a VM.
Since we'r
Implement the hsave MSR, that gives the VCPU a GPA to save the
old guest state in.
Signed-off-by: Alexander Graf <[EMAIL PROTECTED]>
---
arch/x86/kvm/kvm_svm.h |1 +
arch/x86/kvm/svm.c |7 +++
2 files changed, 8 insertions(+), 0 deletions(-)
diff --git a/arch/x86/kvm/kvm_svm.h b/
From: Sheng Yang <[EMAIL PROTECTED]>
EPT is 4 level by default in 32pae(48 bits), but the addr parameter
of kvm_shadow_walk->entry() only accept unsigned long as virtual
address, which is 32bit in 32pae. This result in SHADOW_PT_INDEX()
overflow when try to fetch level 4 index.
Fix it by extend k
Support SR-IOV capability. By default, this feature is not enabled and the
SR-IOV device behaves as traditional PCI device. After it's enabled, each
Virtual Function's PCI configuration space can be accessed using its own Bus,
Device and Function Number (Routing ID). Each Virtual Function also h
Complete the hotplug ABI document, and add SR-IOV HOWTO.
Signed-off-by: Yu Zhao <[EMAIL PROTECTED]>
Signed-off-by: Eddie Dong <[EMAIL PROTECTED]>
---
Documentation/ABI/testing/sysfs-bus-pci | 67
Documentation/DocBook/kernel-api.tmpl |3 +
Documentation/PCI/pci-iov-howto.txt
Some basic changes to allocation bus range, MMIO resource for SR-IOV device.
And add new sysfs entry to hotplug core to pass parameter to a slot, which will
be used by SR-IOV code.
Signed-off-by: Yu Zhao <[EMAIL PROTECTED]>
Signed-off-by: Eddie Dong <[EMAIL PROTECTED]>
---
drivers/pci/bus.c
Support Alternative Routing-ID Interpretation (ARI), which increases the number
of functions that can be supported by a PCIe endpoint. ARI is required by
SR-IOV.
PCI-SIG ARI specification can be found at
http://www.pcisig.com/specifications/pciexpress/specifications/ECN-alt-rid-interpretation-0
Greetings,
Following patches add SR-IOV capability support to the Linux kernel. With these
patches, people can turn a PCI device with the capability into multiple ones
from software perspective.
[PATCH 1/4 v2] PCI: introduce new base functions
[PATCH 2/4 v2] PCI: support ARI capability
[PATCH 3
Cristi Magherusan wrote:
Those who have installed a local DNS server may need that stuff, but we
can check every entries of resolv.conf and see if we can connect to
their DNS server, and use in our VM the first one that could be reached.
The network maybe down when the VM is started, or the
Hello,
On Mon, 2008-09-01 at 13:29 +0300, Avi Kivity wrote:
> What does your /etc/resolv.conf look like?
It used to look like this:
nameserver 127.0.0.1
nameserver
nameserver
Inside the VM the DNS resolver was broken.
After removing that line from the dhclient config now I have only my
real DN
Zhang, Xiantao wrote:
Resend. Privious one forgets to remove debug info. Sorry!
Xiantao
From 8c032c78665745ef421a75d2a9465d392f068c93 Mon Sep 17 00:00:00 2001
From: Xiantao Zhang <[EMAIL PROTECTED]>
Date: Sat, 30 Aug 2008 08:36:03 +0800
Subject: [PATCH] kvm/ia64: Qemu : Add get/set_mpstate for I
Zhang, Xiantao wrote:
From 74cc2bedddc4f97d8901a43d5ac65f938156e2df Mon Sep 17 00:00:00 2001
From: Xiantao Zhang <[EMAIL PROTECTED]>
Date: Thu, 28 Aug 2008 09:34:08 +0800
Subject: [PATCH] KVM/IA64: Implement
kvm_arch_vcpu_ioctl_{set,get}_mpstate.
Two ioctl arch functions are added to set/get vcp
Avi Kivity wrote:
> Farkas Levente wrote:
>>
>> ok this last one was my fault:-(
>> but i retest is again.
>> - kvm-74 with kmod-kvm-74 not working
>> - kvm-71 with kmod-kvm-74 working
>> any progress with this?
>> anyone can test it with a simple minimal mandrake-10 install. after the
>> install t
Charles Duffy wrote:
A few quick notes:
- The extboot.bin regression from kvm-71 (SCSI drives being
unavailable after reboot) is still outstanding.
Now fixed.
- kvm (and presumably qemu) doesn't check for fd= parameters pointing
to file descriptor numbers which are not, in fact, open; t
Iain Paton wrote:
Hi,
Given a kernel tree originally built using the O= method, what's the
suggested
way to build the external modules ?
If the kernel was built, installed, and is now running, ./configure;
make should suffice. I've never tested this though. Have you tried this?
I don
On Mon, Sep 01, 2008 at 12:40:04PM +0300, Avi Kivity wrote:
> Yang, Sheng wrote:
>> From: Sheng Yang <[EMAIL PROTECTED]>
>> Date: Mon, 1 Sep 2008 17:28:59 +0800
>> Subject: [PATCH] KVM: MMU: Fix overflow of SHADOW_PT_INDEX with EPT in 32pae
>>
>> EPT is 4 level by default in 32pae (48bits), but vir
(copying qemu-devel)
Cristi Magherusan wrote:
Hello,
It seems that qemu (and our kvm-qemu branch) and virtualbox suffer of
this issue regarding the DNS resolver:
http://www.virtualbox.org/ticket/421
I know it's mostly a DHCP client config problem, but we could try if the
designated DNS server
Mohammed Gamal wrote:
Adds cld/std, cli/sti, and clc instructions to the test harness.
Applied, thanks.
--
error compiling committee.c: too many arguments to function
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More majord
Mohammed Gamal wrote:
This adds the std and cld instructions to the emulator.
Encountered while running the BIOS with the invalid guest
state emulation patch.
Applied, thanks.
--
error compiling committee.c: too many arguments to function
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To unsubscribe from this list: send the line "u
Hello,
It seems that qemu (and our kvm-qemu branch) and virtualbox suffer of
this issue regarding the DNS resolver:
http://www.virtualbox.org/ticket/421
I know it's mostly a DHCP client config problem, but we could try if the
designated DNS servers are reachable before we pass them to our virtual
Mohammed Gamal wrote:
Save eflags in exec_in_big_real_mode(). This is needed to test instructions that
modify the eflags register.
Applied, thanks.
@@ -82,6 +82,10 @@ static void exec_in_big_real_mode(const struct regs *inregs,
"test_insn: . = . + 16\n\t"
"
Yang, Sheng wrote:
From: Sheng Yang <[EMAIL PROTECTED]>
Date: Mon, 1 Sep 2008 17:28:59 +0800
Subject: [PATCH] KVM: MMU: Fix overflow of SHADOW_PT_INDEX with EPT in 32pae
EPT is 4 level by default in 32pae (48bits), but virtual address only
got 32 bits. This result in SHADOW_PT_INDEX() overflow w
Zhang, Xiantao wrote:
Maybe we can limit it in ia64 side. Program firmware maybe hard to get
check-in, since Xen also share this firmware.
I don't see why initializing pmbase in the firmware should hurt Xen.
The firmware of kvm/ia64 use 0x1f40 as default pm_io_base,
and doesn't have re-c
From: Sheng Yang <[EMAIL PROTECTED]>
Date: Mon, 1 Sep 2008 17:28:59 +0800
Subject: [PATCH] KVM: MMU: Fix overflow of SHADOW_PT_INDEX with EPT in 32pae
EPT is 4 level by default in 32pae (48bits), but virtual address only
got 32 bits. This result in SHADOW_PT_INDEX() overflow when try to
fetch leve
Farkas Levente wrote:
ok this last one was my fault:-(
but i retest is again.
- kvm-74 with kmod-kvm-74 not working
- kvm-71 with kmod-kvm-74 working
any progress with this?
anyone can test it with a simple minimal mandrake-10 install. after the
install the system can't boot.
yours.
Please
Michael Malone wrote:
Hi everyone,
I've written a couple of questions regarding the serial device in
KVM. After slightly more investigation I think I have found what's
going awry. Correct me if I'm wrong, but I believe that KVM generates
an interrupt for every single character it sends thro
Henrik Holst wrote:
> mån 2008-08-25 klockan 18:59 +0200 skrev Farkas Levente:
>
>> the situation is more stranger (but probably another bug)
>> kvm-70 (and kvm-71) with kmod-kvm-73: working if and only if i start
>> mandrake-10 as the first guest, if i start other guest and after i start
>> mandr
Parag Warudkar wrote:
On Sun, Aug 31, 2008 at 11:43 AM, Avi Kivity <[EMAIL PROTECTED]> wrote:
Running an idle Windows VM on Linux 2.6.26+ with kvm, one sees high values
for the kvm process in top (30%-70% cpu), where one would normally expect
0%-1%. Surprisingly, the per-cpu system counters
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