Signed-off-by: Avi Kivity a...@redhat.com
---
hw/onenand.c | 69 +++--
1 files changed, 37 insertions(+), 32 deletions(-)
diff --git a/hw/onenand.c b/hw/onenand.c
index b0cbebc..5b2f01e 100644
--- a/hw/onenand.c
+++ b/hw/onenand.c
@@ -23,6
This tells the sysbus code it need not use IO_MEM_UNASSIGNED.
Signed-off-by: Avi Kivity a...@redhat.com
---
hw/arm11mpcore.c |7 ++-
1 files changed, 6 insertions(+), 1 deletions(-)
diff --git a/hw/arm11mpcore.c b/hw/arm11mpcore.c
index b47707f..7d60ef6 100644
--- a/hw/arm11mpcore.c
+++
Signed-off-by: Avi Kivity a...@redhat.com
---
hw/ppc405_uc.c | 116 ---
1 files changed, 51 insertions(+), 65 deletions(-)
diff --git a/hw/ppc405_uc.c b/hw/ppc405_uc.c
index 06a053b..9caece0 100644
--- a/hw/ppc405_uc.c
+++ b/hw/ppc405_uc.c
@@
Instead, use the bus accessors, or get the address space directly
from the board constructor.
Signed-off-by: Avi Kivity a...@redhat.com
---
hw/cirrus_vga.c | 12 ++--
hw/mips_jazz.c |3 ++-
hw/pc.c |3 ++-
hw/pc.h |5 +++--
hw/qxl.c|2 +-
Signed-off-by: Avi Kivity a...@redhat.com
---
hw/apic.c | 25 ++---
1 files changed, 10 insertions(+), 15 deletions(-)
diff --git a/hw/apic.c b/hw/apic.c
index 9febf40..7d0b0f6 100644
--- a/hw/apic.c
+++ b/hw/apic.c
@@ -80,6 +80,7 @@ typedef struct APICState APICState;
The current implementation of PAM and the PCI holes is broken in several
ways:
- PCI BARs are not restricted to the PCI hole (a BAR may hide memory)
- PCI devices do not respect PAM (if a PCI device maps a region while
PAM maps the region to RAM, the request will be honored)
This patch
Assuming that mmcfg size cannot change at runtime.
Signed-off-by: Avi Kivity a...@redhat.com
---
hw/pcie_host.c | 98 ++-
hw/pcie_host.h | 12 +++---
2 files changed, 31 insertions(+), 79 deletions(-)
diff --git a/hw/pcie_host.c
Not a huge step forward, but at least we now have a 1:1 relationship
between registration and unregistration.
Signed-off-by: Avi Kivity a...@redhat.com
---
hw/ppce500_pci.c | 12 +++-
1 files changed, 11 insertions(+), 1 deletions(-)
diff --git a/hw/ppce500_pci.c b/hw/ppce500_pci.c
A helper that returns the address space used by ISA devices. Useful
for getting rid of isa_mem_base, multiple ISA buses, or ISA buses behind
bridges.
Signed-off-by: Avi Kivity a...@redhat.com
---
hw/isa-bus.c |6 ++
hw/isa.h |1 +
2 files changed, 7 insertions(+), 0 deletions(-)
Signed-off-by: Avi Kivity a...@redhat.com
---
hw/armv7m.c | 24 ++--
1 files changed, 10 insertions(+), 14 deletions(-)
diff --git a/hw/armv7m.c b/hw/armv7m.c
index 83f3393..a932f16 100644
--- a/hw/armv7m.c
+++ b/hw/armv7m.c
@@ -106,31 +106,27 @@ static void
Signed-off-by: Avi Kivity a...@redhat.com
---
hw/apb_pci.c | 84 +
1 files changed, 37 insertions(+), 47 deletions(-)
diff --git a/hw/apb_pci.c b/hw/apb_pci.c
index 1638226..6ee2068 100644
--- a/hw/apb_pci.c
+++ b/hw/apb_pci.c
@@ -31,7
This problem with this function is that it is not reversible - it is
impossible to know where things are registered and unregister them
exactly. As there are no more users, we can remove it.
Signed-off-by: Avi Kivity a...@redhat.com
---
hw/sysbus.c | 12
hw/sysbus.h |2 --
2
Returns the PCI address space. Useful for bridges that can obscure
part of the PCI address space.
Signed-off-by: Avi Kivity a...@redhat.com
---
hw/pci.c |5 +
hw/pci.h |1 +
2 files changed, 6 insertions(+), 0 deletions(-)
diff --git a/hw/pci.c b/hw/pci.c
index dc7271a..4e495b4
Signed-off-by: Avi Kivity a...@redhat.com
---
hw/arm_timer.c | 55 ---
1 files changed, 20 insertions(+), 35 deletions(-)
diff --git a/hw/arm_timer.c b/hw/arm_timer.c
index fd9448f..457736b 100644
--- a/hw/arm_timer.c
+++ b/hw/arm_timer.c
@@
This patchset converts a few more devices (and boards) to the memory API.
Nothing is really interesting except for the last patch, which brings
proper PAM support (and better SMRAM emulation). It should also fix the
regressions that were reported in some non-default pc configurations.
The
Clumsy due to the lack of clipping support, needed for
changing exposed ram size.
Signed-off-by: Avi Kivity a...@redhat.com
---
hw/ppc405.h|9 ++---
hw/ppc405_boards.c | 18 +-
hw/ppc405_uc.c | 12
hw/ppc440.c|7 +--
On 8/8/2011 12:31 AM, Liu Yuan wrote:
On 08/08/2011 01:04 PM, Badari Pulavarty wrote:
On 8/7/2011 6:35 PM, Liu Yuan wrote:
On 08/06/2011 02:02 AM, Badari Pulavarty wrote:
On 8/5/2011 4:04 AM, Liu Yuan wrote:
On 08/05/2011 05:58 AM, Badari Pulavarty wrote:
Hi Liu Yuan,
I started testing
On 8 August 2011 18:06, Avi Kivity a...@redhat.com wrote:
Somewhat clumsy since it needs a variable sized region.
@@ -119,7 +120,7 @@ void omap_sdrc_reset(struct omap_sdrc_s *s);
struct omap_gpmc_s;
struct omap_gpmc_s *omap_gpmc_init(target_phys_addr_t base, qemu_irq irq);
void
* Don Dutile (ddut...@redhat.com) wrote:
On 07/24/2011 06:58 AM, Michael S. Tsirkin wrote:
On Sun, Jul 24, 2011 at 11:41:10AM +0300, Michael S. Tsirkin wrote:
On Sun, Jul 24, 2011 at 11:12:44AM +0300, Michael S. Tsirkin wrote:
On Fri, Jul 22, 2011 at 02:35:47PM -0700, Chris Wright wrote:
*
On Jul 21, 2011, at 2:10 AM, Avi Kivity wrote:
On 07/21/2011 02:20 AM, John Paul Walters wrote:
Hi,
We have a 256 core SGI Ultraviolet machine running RHEL 6.1 with qemu-kvm
0.13, and we'd like to be able to start large guest VMs of up to 256 cores.
I see that x86 guests are currently
On 08/08/2011 06:59 PM, Anthony Liguori wrote:
On 08/08/2011 10:36 AM, Avi Kivity wrote:
On 08/08/2011 06:29 PM, Anthony Liguori wrote:
- Efficient, reduce needed traffic no need to re-send pages.
It's not quite that simple. Post-copy needs to introduce a protocol
capable of requesting
On 08/05/2011 03:55 PM, Marcelo Tosatti wrote:
The following changes since commit 35d7ace74bd07e3d6983c1fd7cbfab4e11175689:
qcow2: Fix L1 table size after bdrv_snapshot_goto (2011-08-05 07:15:47 -0500)
are available in the git repository at:
On 08/08/2011 04:40 AM, Yaniv Kaul wrote:
On 08/08/2011 12:20, Dor Laor wrote:
On 08/08/2011 06:24 AM, Isaku Yamahata wrote:
Design/Implementation
=
The basic idea of postcopy livemigration is to use a sort of distributed
shared memory between the migration source and
The following series implements KVM support for ARM processors,
specifically on the Cortex A-15 platform.
The patch series applies to the arm-lpae branch of ARM Ltd's kernel
tree. This is Version 4 of the patch series, but the first two versions
were reviewed outside of the KVM mailing list.
Targets KVM support for Cortex A-15 processors.
Contains no real functionality but all the framework components,
make files, header files and some tracing functionality.
Most functionality is in arch/arm/kvm/* or arch/arm/include/asm/kvm_*.h.
Signed-off-by: Christoffer Dall
Adds support in the identity mapping feature that allows KVM to setup
identity mapping for the Hyp mode with the AP[1] bit set as required by
the specification and also supports freeing created sub pmd's after
finished use.
These two functions:
- hyp_identity_mapping_add(pgd, addr, end);
-
Sets up the required registers to run code in HYP-mode from the kernel.
No major controversies, but we should consider how to deal with SMP
support for hypervisor stack page.
By setting the HVBAR the kernel can execute code in Hyp-mode with
the MMU disabled. The HVBAR initially points to
This commit introduces the framework for guest memory management
through the use of 2nd stage translation. Each VM has a pointer
to a level-1 tabled (the pgd field in struct kvm_arch) which is
used for the 2nd stage translations. Entries are added when handling
guest faults (later patch) and the
Userspace can inject IRQs and FIQs through the KVM_IRQ_LINE VM ioctl.
This ioctl is used since the sematics are in fact two lines that can be
either raised or lowered on the VCPU - the IRQ and FIQ lines.
KVM needs to know which VCPU it must operate on and whether the FIQ or
IRQ line is
Provides complete world-switch implementation to switch to other guests
runinng in non-secure modes. Includes Hyp exception handlers that
captures necessary exception information and stores the information on
the VCPU and KVM structures.
Switching to Hyp mode is done through a simple HVC
Adds a new important function in the main KVM/ARM code called
handle_exit() which is called from kvm_arch_vcpu_ioctl_run() on returns
from guest execution. This function examines the Hyp-Syndrome-Register
(HSR), which contains information telling KVM what caused the exit from
the guest.
Some of
Handles the guest faults in KVM by mapping in corresponding user pages
in the 2nd stage page tables.
Introduces new ARM-specific kernel memory types, PAGE_KVM_GUEST and
pgprot_guest variables used to map 2nd stage memory for KVM guests.
Signed-off-by: Christoffer Dall
When the guest accesses I/O memory this will create data abort
exceptions and they are handled by decoding the HSR information
(physical address, read/write, length, register) and forwarding reads
and writes to QEMU which performs the device emulation.
Certain classes of load/store operations do
When the guest executes a WFI instruction the operation is trapped to
KVM, which emulates the instruction in software. There is no correlation
between a guest executing a WFI instruction and actually puttin the
hardware into a low-power mode, since a KVM guest is essentially a
process and the WFI
Is that a pointer to the coding standards used for the kvm tools?
Thanks,
\dae
--
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On Mon, Aug 08, 2011 at 10:47:09PM +0300, Dor Laor wrote:
On 08/08/2011 06:59 PM, Anthony Liguori wrote:
On 08/08/2011 10:36 AM, Avi Kivity wrote:
On 08/08/2011 06:29 PM, Anthony Liguori wrote:
- Efficient, reduce needed traffic no need to re-send pages.
It's not quite that simple.
On Mon, Aug 08, 2011 at 03:38:54PM +0300, Avi Kivity wrote:
On 08/08/2011 06:24 AM, Isaku Yamahata wrote:
This mail is on Yabusame: Postcopy Live Migration for Qemu/KVM
on which we'll give a talk at KVM-forum.
The purpose of this mail is to letting developers know it in advance
so that we can
msa.hinet.net
123.223.195.63attachment: Aflrwc_3509.gif
The main goal of the patch is to effectively cap the disk I/O speed or counts
of one single VM.It is only one draft, so it unavoidably has some drawbacks, if
you catch them, please let me know.
The patch will mainly introduce one block I/O throttling algorithm, one timer
and one block queue
Signed-off-by: Zhi Yong Wu wu...@linux.vnet.ibm.com
---
Makefile.objs |2 +-
blockdev.c | 39 +++
qemu-config.c | 24
qemu-option.c | 17 +
qemu-option.h |1 +
qemu-options.hx |1 +
6 files
The patch introduce one block queue for QEMU block layer.
Signed-off-by: Zhi Yong Wu wu...@linux.vnet.ibm.com
---
block/blk-queue.c | 141 +
block/blk-queue.h | 73 +++
2 files changed, 214 insertions(+), 0
Note:
1.) When bps/iops limits are specified to a small value such as 511
bytes/s, this VM will hang up. We are considering how to handle this senario.
2.) When dd command is issued in guest, if its option bs is set to a
large value such as bs=1024K, the result speed will slightly
The patch introduce one new command block_set_io_throttle; For its usage
syntax, if you have better idea, pls let me know.
Signed-off-by: Zhi Yong Wu wu...@linux.vnet.ibm.com
---
blockdev.c | 69 +++
blockdev.h |2 +
On Mon, 2011-08-08 at 16:59 -0700, David Evensky wrote:
Is that a pointer to the coding standards used for the kvm tools?
Thanks,
\dae
kvm tools basically follows the kernel coding style.
Documentation for it can be found in /Documentation/CodingStyle under
your kernel tree (or here:
On Mon, 2011-08-08 at 16:59 -0700, David Evensky wrote:
Is that a pointer to the coding standards used for the kvm tools?
Thanks,
\dae
On Tue, Aug 9, 2011 at 8:50 AM, Sasha Levin levinsasha...@gmail.com wrote:
kvm tools basically follows the kernel coding style.
Documentation for it can be
On Mon, Jul 25, 2011 at 11:50:50PM +0200, Alexander Graf wrote:
On 25.07.2011, at 21:25, Scott Wood wrote:
On Sun, 24 Jul 2011 11:16:32 +0200
Alexander Graf ag...@suse.de wrote:
On 19.07.2011, at 13:20, Johannes Weiner wrote:
You don't have to work around the mm subsystem trying
On 08/08/2011 03:49 AM, Johannes Weiner wrote:
On Mon, Jul 25, 2011 at 11:50:50PM +0200, Alexander Graf wrote:
Well, alternatively we could simply bail out if the memory is not
anonymous, right? Then the pinning on get_user_pages_fast should be
enough. Johannes, would there be any downside to
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