On 05/03/2012 03:56 PM, Michael S. Tsirkin wrote:
On Thu, May 03, 2012 at 03:30:47PM +0800, Asias He wrote:
If we reset the virtio-blk device before the requests already dispatched
to the virtio-blk driver from the block layer are finised, we will stuck
in blk_cleanup_queue() and the remove
If we reset the virtio-blk device before the requests already dispatched
to the virtio-blk driver from the block layer are finised, we will stuck
in blk_cleanup_queue() and the remove will fail.
blk_cleanup_queue() calls blk_drain_queue() to drain all requests queued
before DEAD marking. However
* Nikunj A. Dadhania nik...@linux.vnet.ibm.com [2012-04-27 21:54:37]:
@@ -1549,6 +1549,11 @@ static void kvm_set_vcpu_state(struct kvm_vcpu *vcpu)
return;
vs-state = 1;
+ if (vs-flush_on_enter) {
+ kvm_mmu_flush_tlb(vcpu);
+
Add support to the MMX versions of the movq instructions to
the instruction emulator. Also handle possible exceptions
they may cause.
Signed-off-by: Joerg Roedel joerg.roe...@amd.com
---
arch/x86/include/asm/kvm_emulate.h |2 +-
arch/x86/kvm/emulate.c | 155
If we reset the virtio-blk device before the requests already dispatched
to the virtio-blk driver from the block layer are finised, we will stuck
in blk_cleanup_queue() and the remove will fail.
blk_cleanup_queue() calls blk_drain_queue() to drain all requests queued
before DEAD marking. However
This adds a new ioctl to enable userspace to control the size of the guest
hashed page table (HPT) and to clear it out when resetting the guest.
The KVM_PPC_ALLOCATE_HTAB ioctl is a VM ioctl and takes as its parameter
a pointer to a u32 containing the desired order of the HPT (log base 2
of the
When reading and writing SPRs, every SPR emulation piece had to read
or write the respective GPR the value was read from or stored in itself.
This approach is pretty prone to failure. What if we accidentally
implement mfspr emulation where we just do break and nothing else?
Suddenly we would get
Instructions on PPC are pretty similarly encoded. So instead of
every instruction emulation code decoding the instruction fields
itself, we can move that code to more generic places and rely on
the compiler to optimize the unused bits away.
This has 2 advantages. It makes the code smaller and it
Signed-off-by: Jiří Župka jzu...@redhat.com
---
client/virt/virt_utils.py | 47 +++-
1 files changed, 33 insertions(+), 14 deletions(-)
diff --git a/client/virt/virt_utils.py b/client/virt/virt_utils.py
index 0ac52d8..7c92068 100644
---
This test starts vm on master host. When vm is started then it starts file
transfer between vm and master host:
work: migration:
host1-vmmig_1(host1-host2)
vm-host1
checksum file
host1-vm
vm-host1
On Fri, May 04, 2012 at 04:37:45PM +0800, Asias He wrote:
On 05/03/2012 03:56 PM, Michael S. Tsirkin wrote:
On Thu, May 03, 2012 at 03:30:47PM +0800, Asias He wrote:
If we reset the virtio-blk device before the requests already dispatched
to the virtio-blk driver from the block layer are
When instruction decoding begins there could be stale values
in the ctxt-memop structure. This causes problems when an
instruction is emulated with more op-bytes then the guest
wants (like the bsr instruction which is always emulated
with 4 or 8 op-bytes).
The stale value in this structure causes
I've been working on adding an IPMI BMC as a virtual device under KVM. I'm
doing this for two primary reasons, one to have a better test
environment than
what I have now for testing IPMI issues, and second to be able to better
simulate a legacy environment for customers porting legacy
Hi All,
This is KVM upstream test result against kvm.git
95f714727436836bb46236ce2bcd8ee8f9274aed based on kernel 3.4.0-rc4, and
qemu-kvm.git b320b8b70bd4f5f6800b85bc95981a8ed09f943c.
We found 1 new bug and 1 bug got fixed in the past two weeks.
New issue (1):
1. (Nested-virt) L1 (kvm on
This adds a new ioctl to enable userspace to control the size of the guest
hashed page table (HPT) and to clear it out when resetting the guest.
The KVM_PPC_ALLOCATE_HTAB ioctl is a VM ioctl and takes as its parameter
a pointer to a u32 containing the desired order of the HPT (log base 2
of the
When reading and writing SPRs, every SPR emulation piece had to read
or write the respective GPR the value was read from or stored in itself.
This approach is pretty prone to failure. What if we accidentally
implement mfspr emulation where we just do break and nothing else?
Suddenly we would get
Instructions on PPC are pretty similarly encoded. So instead of
every instruction emulation code decoding the instruction fields
itself, we can move that code to more generic places and rely on
the compiler to optimize the unused bits away.
This has 2 advantages. It makes the code smaller and it
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