The Buildbot has detected a new failure on builder ppc64 while building kvm.
Full details are available at:
http://buildbot.b1-systems.de/kvm/builders/ppc64/builds/582
Buildbot URL: http://buildbot.b1-systems.de/kvm/
Buildslave for this Build: b1_kvm_1
Build Reason: The Nightly scheduler named
The Buildbot has detected a new failure on builder ppc44x while building kvm.
Full details are available at:
http://buildbot.b1-systems.de/kvm/builders/ppc44x/builds/585
Buildbot URL: http://buildbot.b1-systems.de/kvm/
Buildslave for this Build: b1_kvm_1
Build Reason: The Nightly scheduler
Flush pending coalesced MMIO before performing mapping or state changes
that could affect the event orderings or route the buffered requests to
a wrong region.
Signed-off-by: Jan Kiszka jan.kis...@siemens.com
In addition, we also have to
---
memory.c | 23 +++
1 files
In preparation of stopping to flush coalesced MMIO unconditionally on
vmexits, mark VGA MMIO and PIO regions as synchronous /wrt coalesced
MMIO and flush the buffer explicitly on PIO accesses that do not use
generic memory regions yet.
Signed-off-by: Jan Kiszka jan.kis...@siemens.com
---
Instead of flushing pending coalesced MMIO requests on every vmexit,
this provides a mechanism to selectively flush when memory regions
related to the coalesced one are accessed. This first of all includes
the coalesced region itself but can also applied to other regions, e.g.
of the same device,
The memory subsystem will now take care of flushing whenever affected
regions are accessed or the memory mapping changes.
Signed-off-by: Jan Kiszka jan.kis...@siemens.com
---
kvm-all.c |2 --
1 files changed, 0 insertions(+), 2 deletions(-)
diff --git a/kvm-all.c b/kvm-all.c
index
We currently flush the coalesced MMIO buffer on every vmexit to
userspace. KVM only provides a single buffer per VM, so a central lock
is required to read from it. This is a contention point given a large
enough VCPU set. Moreover, we need to hold the BQL while replaying the
queued requests,
This MMIO area is an entry gate to legacy PC ISA devices, addressed via
PIO over there. Quite a few of the PIO ports have side effects on access
like starting/stopping timers that must be executed properly ordered
/wrt the CPU. So we have to remove the coalescing mark.
CC: Andreas Färber
Jan Kiszka a écrit :
This MMIO area is an entry gate to legacy PC ISA devices, addressed via
PIO over there. Quite a few of the PIO ports have side effects on access
like starting/stopping timers that must be executed properly ordered
/wrt the CPU. So we have to remove the coalescing mark.
CC:
Am 25.06.2012 09:11, schrieb Hervé Poussineau:
Jan Kiszka a écrit :
This MMIO area is an entry gate to legacy PC ISA devices, addressed via
PIO over there. Quite a few of the PIO ports have side effects on access
like starting/stopping timers that must be executed properly ordered
/wrt the
On 06/25/2012 10:00 AM, Jan Kiszka wrote:
Instead of flushing pending coalesced MMIO requests on every vmexit,
this provides a mechanism to selectively flush when memory regions
related to the coalesced one are accessed. This first of all includes
the coalesced region itself but can also
Am 25.06.2012 09:01, schrieb Jan Kiszka:
Flush pending coalesced MMIO before performing mapping or state changes
that could affect the event orderings or route the buffered requests to
a wrong region.
Signed-off-by: Jan Kiszka jan.kis...@siemens.com
In addition, we also have to
Stray
On 06/25/2012 10:01 AM, Jan Kiszka wrote:
Flush pending coalesced MMIO before performing mapping or state changes
that could affect the event orderings or route the buffered requests to
a wrong region.
Signed-off-by: Jan Kiszka jan.kis...@siemens.com
In addition, we also have to
Yes, we
On 06/25/2012 09:33 AM, k...@buildbot.b1-systems.de wrote:
The Buildbot has detected a new failure on builder ppc64 while building kvm.
Full details are available at:
http://buildbot.b1-systems.de/kvm/builders/ppc64/builds/582
Buildbot URL: http://buildbot.b1-systems.de/kvm/
Buildslave
From: Krishna Kumar krkum...@in.ibm.com
Introduce VIRTIO_NET_F_MULTIQUEUE.
Signed-off-by: Krishna Kumar krkum...@in.ibm.com
Signed-off-by: Jason Wang jasow...@redhat.com
---
include/linux/virtio_net.h |1 +
1 files changed, 1 insertions(+), 0 deletions(-)
diff --git
Instead of storing the queue index in virtio infos, this patch moves them to
vring_virtqueue and introduces helpers to set and get the value. This would
simplify the management and tracing.
Signed-off-by: Jason Wang jasow...@redhat.com
---
drivers/virtio/virtio_mmio.c |5 +
Hello All:
This series is an update version of multiqueue virtio-net driver based on
Krishna Kumar's work to let virtio-net use multiple rx/tx queues to do the
packets reception and transmission. Please review and comments.
Test Environment:
- Intel(R) Xeon(R) CPU E5620 @ 2.40GHz, 8 cores 2 numa
On 2012-06-11 13:19, Michael S. Tsirkin wrote:
We can deliver certain interrupts, notably MSIX,
from atomic context.
Here's an untested patch to do this (compiled only).
Changes from v2:
Don't inject broadcast interrupts directly
Changes from v1:
Tried to address comments from v1, except
On 06/24/2012 07:24 PM, Michael S. Tsirkin wrote:
I'm looking at reducing the interrupt overhead for virtualized guests:
some workloads spend a large part of their time processing interrupts.
On kvm, an EOI write from the guest causes an expensive exit to host; we
avoid this using shared
Device specific irq optimizations such as irq affinity may be used by virtio
drivers. So this patch introduce a new method to get the irq of a specific
virtqueue.
After this patch, virtio device drivers could query the irq and do device
specific optimizations. First user would be virtio-net.
This addes multiqueue support to virtio_net driver. This feature is negotiated
through VIRTIO_NET_F_MULTIQUEUE.
The driver expects the number of rx/tx queue paris is equal to the number of
vcpus. To maximize the performance under this per-cpu rx/tx queue pairs, some
optimization were introduced:
On Mon, Jun 25, 2012 at 05:16:48PM +0800, Jason Wang wrote:
Hello All:
This series is an update version of multiqueue virtio-net driver based on
Krishna Kumar's work to let virtio-net use multiple rx/tx queues to do the
packets reception and transmission. Please review and comments.
Test
Hello all:
This seires is an update of last version of multiqueue support to add multiqueue
capability to both tap and virtio-net.
Some kinds of tap backends has (macvatp in linux) or would (tap) support
multiqueue. In such kind of tap backend, each file descriptor of a tap is a
qeueu and ioctls
Sometimes, we need to pass option like -netdev tap,fd=100,fd=101,fd=102 which
can not be properly parsed by qemu_find_opt() because it only returns the first
matched option. So qemu_get_opt_all() were introduced to return an array of
pointers which contains all matched option.
Signed-off-by:
This patch adds basic support for the multiple queue capable tap device. When
multiqueue were enabled for a tap device, user can attach/detach multiple files
(sockets) to the device through TUNATTACHQUEUE/TUNDETACHQUEUE.
Two helpers tun_attach() and tun_deatch() were introduced to attach and
This patch adds the multiqueues support for emulated nics. Each VLANClientState
pairs are now abstract as a queue instead of a nic, and multiple VLANClientState
pointers were stored in the NICState. A queue_index were also introduced to let
the emulated nics know which queue the packet were came
This patch let the virtio-net can transmit and recevie packets through multiuple
VLANClientStates and abstract them as multiple virtqueues to guest. A new
parameter 'queues' were introduced to specify the number of queue pairs.
The main goal for vhost support is to let the multiqueue could be
On Mon, Jun 25, 2012 at 05:41:17PM +0800, Jason Wang wrote:
Device specific irq optimizations such as irq affinity may be used by virtio
drivers. So this patch introduce a new method to get the irq of a specific
virtqueue.
After this patch, virtio device drivers could query the irq and do
On 2012-06-25 10:57, Avi Kivity wrote:
On 06/25/2012 10:01 AM, Jan Kiszka wrote:
Flush pending coalesced MMIO before performing mapping or state changes
that could affect the event orderings or route the buffered requests to
a wrong region.
Signed-off-by: Jan Kiszka jan.kis...@siemens.com
On 2012-06-25 12:15, Jan Kiszka wrote:
On 2012-06-25 10:57, Avi Kivity wrote:
The repetitiveness of this code suggests a different way of doing this:
make every API call be its own subtransaction and perform the flush in
memory_region_begin_transaction() (maybe that's the answer to my
On Sat, Jun 23, 2012 at 7:08 AM, Emmanuel Noobadmin
centos.ad...@gmail.com wrote:
On 6/22/12, Stefan Hajnoczi stefa...@gmail.com wrote:
Thanks for investigating and sharing the information you've found.
It's archived on the list so anyone who hits it in the future or wants
to reproduce it can
On 06/25/2012 01:26 PM, Jan Kiszka wrote:
On 2012-06-25 12:15, Jan Kiszka wrote:
On 2012-06-25 10:57, Avi Kivity wrote:
The repetitiveness of this code suggests a different way of doing this:
make every API call be its own subtransaction and perform the flush in
On 25.06.2012, at 11:07, Avi Kivity wrote:
On 06/25/2012 09:33 AM, k...@buildbot.b1-systems.de wrote:
The Buildbot has detected a new failure on builder ppc64 while building kvm.
Full details are available at:
http://buildbot.b1-systems.de/kvm/builders/ppc64/builds/582
Buildbot URL:
On 2012-06-25 13:01, Avi Kivity wrote:
On 06/25/2012 01:26 PM, Jan Kiszka wrote:
On 2012-06-25 12:15, Jan Kiszka wrote:
On 2012-06-25 10:57, Avi Kivity wrote:
The repetitiveness of this code suggests a different way of doing this:
make every API call be its own subtransaction and perform the
Hi all,
I am freshman to this community, I have some questions roughly about how
does KVM work, please help me answer these questions, thank you!
1, What is the relation between kvm-mod and kvm-qemu?
Is kvm-qemu mainly used to emulate the first initial 16-bit code of a
guest, then this qemu
On Mon, Jun 25, 2012 at 07:55:55AM +0200, Andreas Hartmann wrote:
Hello Joerg,
Joerg Roedel wrote:
On Tue, Jun 05, 2012 at 08:27:05AM -0600, Alex Williamson wrote:
Joerg, the question is whether the multifunction device above allows
peer-to-peer between functions that could bypass the
On Mon, 2012-06-25 at 13:03 +0200, Alexander Graf wrote:
On 25.06.2012, at 11:07, Avi Kivity wrote:
On 06/25/2012 09:33 AM, k...@buildbot.b1-systems.de wrote:
The Buildbot has detected a new failure on builder ppc64 while building
kvm.
Full details are available at:
Machine check exception handler was using a wrong prolog. Hypervisors, like
KVM, which are called early from the exception handler rely on the interrupt
source.
Signed-off-by: Mihai Caraman mihai.cara...@freescale.com
---
arch/powerpc/kernel/exceptions-64e.S |2 +-
1 files changed, 1
Embedded.Hypervisor category defines GSPRG0..3 physical registers for guests.
Avoid SPRG4-7 usage as scratch in host exception handlers, otherwise guest
SPRG4-7 registers will be clobbered.
For bolted TLB miss exception handlers, which is the version currently
supported by KVM, use
Add KVM_SREGS_E_64 feature and EPCR spr support in get/set sregs
for 64-bit hosts.
Signed-off-by: Mihai Caraman mihai.cara...@freescale.com
---
arch/powerpc/kvm/booke.c | 14 ++
1 files changed, 14 insertions(+), 0 deletions(-)
diff --git a/arch/powerpc/kvm/booke.c
64-bit host needs to remain in 64-bit mode when an exception take place.
Set interrupt computaion mode in EPCR register.
Signed-off-by: Mihai Caraman mihai.cara...@freescale.com
---
arch/powerpc/kvm/e500mc.c |5 -
1 files changed, 4 insertions(+), 1 deletions(-)
diff --git
Add emulation helper for getting instruction ea and refactor tlb instruction
emulation to use it.
Signed-off-by: Mihai Caraman mihai.cara...@freescale.com
---
arch/powerpc/kvm/e500.h |6 +++---
arch/powerpc/kvm/e500_emulate.c | 21 ++---
arch/powerpc/kvm/e500_tlb.c
Hook DO_KVM macro to 64-bit booke in a optimal way similar to 32-bit booke
see head_fsl_booke.S file. Extend interrupt handlers' parameter list with
interrupt vector numbers to accomodate the macro. Rework Guest Doorbell
handler to use the proper GSRRx save/restore registers.
Only the bolted
Add bookehv interrupt handling support for 64-bit hosts. Change common stack
layout to refer PPC_LR_STKOFF kernel constant. Dispatch the 64-bit execution
flow to the existing kvm_handler_common asm macro. Update input register
values documentation.
Only the bolted version of TLB miss exception
64-bit host runs with lazy interrupt disabling, so local_irq_disable() does
not disable interrupts right away and does not protect against preemption
required by __kvmppc_vcpu_run(). Define a macro for 64-bit to use
hard_irq_disable().
Signed-off-by: Mihai Caraman mihai.cara...@freescale.com
---
This patchset adds 64-bit Book3E PowerPC support to KVM. It is intended
as a request for comment for scratch register changes and for the support
limited to bolted TLB miss exception handlers.
This work was validated on Freescale's e5500 cores using P5020DS boards.
This patchset is based on Alex
When delivering guest IRQs, update MSR computaion mode according to guest
interrupt computation mode found in EPCR.
Signed-off-by: Mihai Caraman mihai.cara...@freescale.com
---
arch/powerpc/kvm/booke.c |8 +++-
1 files changed, 7 insertions(+), 1 deletions(-)
diff --git
Include header file for get_tb() declaration.
Signed-off-by: Mihai Caraman mihai.cara...@freescale.com
---
arch/powerpc/kvm/booke.c |1 +
1 files changed, 1 insertions(+), 0 deletions(-)
diff --git a/arch/powerpc/kvm/booke.c b/arch/powerpc/kvm/booke.c
index db05692..a427031 100644
---
Add EPCR support in booke mtspr/mfspr emulation. EPCR register is defined
only for 64-bit and HV categories, so it shoud be available only on 64-bit
virtual processors. Undefine the support for 32-bit builds.
Define a reusable setter function for vcpu's EPCR.
Signed-off-by: Mihai Caraman
GET_VCPU define will not be implemented for 64-bit for performance reasons
so get rid of it also on 32-bit.
Signed-off-by: Mihai Caraman mihai.cara...@freescale.com
---
arch/powerpc/kvm/bookehv_interrupts.S |7 ++-
1 files changed, 2 insertions(+), 5 deletions(-)
diff --git
Refactor exception prolog to allow save/restore register parameters. Add
addition none definition for exception prolog usage.
This is needed for exceptions like Guest Doorbell that use GSRRx regsiters
which do not map on exception type.
Signed-off-by: Mihai Caraman mihai.cara...@freescale.com
---
Mask high 32 bits of effective address in emulation layer, for guests running
in 32-bit mode.
MAS2's high-order 32 bits represents the upper 32 bits of the effective address
of the page. Mask it too for tlbwe instruction emulation.
Signed-off-by: Mihai Caraman mihai.cara...@freescale.com
---
Extend MAS2 EPN mask for 64-bit hosts, to retain most significant bits.
Change get tlb eaddr to use this mask.
Signed-off-by: Mihai Caraman mihai.cara...@freescale.com
---
arch/powerpc/include/asm/mmu-book3e.h |2 +-
arch/powerpc/kvm/e500.h |2 +-
2 files changed, 2
tlbilxva emulation was using an u32 variable for guest effective address.
Replace it with gva_t type to handle 64-bit guests.
Signed-off-by: Mihai Caraman mihai.cara...@freescale.com
---
arch/powerpc/kvm/e500mc.c |3 ++-
1 files changed, 2 insertions(+), 1 deletions(-)
diff --git
64-bit GCC 4.5.1 warns about an uninitialized variable which was guarded
by a flag. Initialize the variable to make it happy.
Signed-off-by: Mihai Caraman mihai.cara...@freescale.com
---
arch/powerpc/kvm/e500_tlb.c |3 ++-
1 files changed, 2 insertions(+), 1 deletions(-)
diff --git
On 06/24/2012 05:27 PM, Gleb Natapov wrote:
On Sun, Jun 24, 2012 at 04:39:22PM +0300, Avi Kivity wrote:
On 06/24/2012 04:27 PM, Gleb Natapov wrote:
On Sun, Jun 24, 2012 at 04:12:05PM +0300, Avi Kivity wrote:
On 06/12/2012 03:01 PM, Gleb Natapov wrote:
The function will be used outside of
On 06/25/2012 03:26 PM, Mihai Caraman wrote:
Add KVM_SREGS_E_64 feature and EPCR spr support in get/set sregs
for 64-bit hosts.
Signed-off-by: Mihai Caraman mihai.cara...@freescale.com
---
arch/powerpc/kvm/booke.c | 14 ++
1 files changed, 14 insertions(+), 0 deletions(-)
On Mon, Jun 25, 2012 at 03:57:42PM +0300, Avi Kivity wrote:
On 06/24/2012 05:27 PM, Gleb Natapov wrote:
On Sun, Jun 24, 2012 at 04:39:22PM +0300, Avi Kivity wrote:
On 06/24/2012 04:27 PM, Gleb Natapov wrote:
On Sun, Jun 24, 2012 at 04:12:05PM +0300, Avi Kivity wrote:
On 06/12/2012 03:01
-Original Message-
From: Avi Kivity [mailto:a...@redhat.com]
Sent: Monday, June 25, 2012 4:00 PM
To: Caraman Mihai Claudiu-B02008
Cc: kvm-...@vger.kernel.org; kvm@vger.kernel.org; linuxppc-
d...@lists.ozlabs.org; qemu-...@nongnu.org
Subject: Re: [RFC PATCH 03/17] KVM: PPC64: booke:
On 06/25/2012 04:24 PM, Caraman Mihai Claudiu-B02008 wrote:
-Original Message-
From: Avi Kivity [mailto:a...@redhat.com]
Sent: Monday, June 25, 2012 4:00 PM
To: Caraman Mihai Claudiu-B02008
Cc: kvm-...@vger.kernel.org; kvm@vger.kernel.org; linuxppc-
d...@lists.ozlabs.org;
https://bugzilla.kernel.org/show_bug.cgi?id=42782
Reartes Guillermo rtgui...@gmail.com changed:
What|Removed |Added
CC||rtgui...@gmail.com
On Mon, 2012-05-14 at 18:07 -0300, Jan Kiszka wrote:
Add a service that establishes a static route from a virtual IRQ line to
an MSI message. Will be used for IRQFD and device assignment. As we will
use this service outside of CONFIG_KVM protected code, stub it properly.
Signed-off-by: Jan
On 06/25/2012 04:12 PM, Gleb Natapov wrote:
Right. But I think we can have x86_linearize() that doesn't take a
context parameter, only ops.
All ops take context parameter though.
context is meaningful for:
- saving state between executions (decode/execute/execute)
- passing state that is
https://bugzilla.kernel.org/show_bug.cgi?id=42782
--- Comment #6 from Reartes Guillermo rtgui...@gmail.com 2012-06-25 13:50:00
---
Created an attachment (id=74211)
-- (https://bugzilla.kernel.org/attachment.cgi?id=74211)
dmesg at poweron, with page fault
--
Configure bugmail:
https://bugzilla.kernel.org/show_bug.cgi?id=42782
--- Comment #7 from Reartes Guillermo rtgui...@gmail.com 2012-06-25 13:50:24
---
Created an attachment (id=74221)
-- (https://bugzilla.kernel.org/attachment.cgi?id=74221)
dmesg when reset, no page fault
--
Configure bugmail:
On 2012-06-25 15:38, Alex Williamson wrote:
On Mon, 2012-05-14 at 18:07 -0300, Jan Kiszka wrote:
Add a service that establishes a static route from a virtual IRQ line to
an MSI message. Will be used for IRQFD and device assignment. As we will
use this service outside of CONFIG_KVM protected
https://bugzilla.kernel.org/show_bug.cgi?id=42782
--- Comment #8 from Reartes Guillermo rtgui...@gmail.com 2012-06-25 13:52:18
---
Created an attachment (id=74231)
-- (https://bugzilla.kernel.org/attachment.cgi?id=74231)
lspci -vvvnn
--
Configure bugmail:
https://bugzilla.kernel.org/show_bug.cgi?id=42782
--- Comment #9 from Joerg Roedel j...@8bytes.org 2012-06-25 14:06:54 ---
The addresses where the page-fault happens look strange: 0xf00420800.
This address is beyond TOM2 which means it does not point to system RAM. To me
this looks like
On 6/25/2012 3:07 AM, Michael S. Tsirkin wrote:
On Mon, Jun 25, 2012 at 05:16:48PM +0800, Jason Wang wrote:
Hello All:
This series is an update version of multiqueue virtio-net driver based on
Krishna Kumar's work to let virtio-net use multiple rx/tx queues to do the
packets reception and
On Mon, Jun 25, 2012 at 04:40:35PM +0300, Avi Kivity wrote:
On 06/25/2012 04:12 PM, Gleb Natapov wrote:
Right. But I think we can have x86_linearize() that doesn't take a
context parameter, only ops.
All ops take context parameter though.
context is meaningful for:
- saving
https://bugzilla.kernel.org/show_bug.cgi?id=42782
--- Comment #10 from Reartes Guillermo rtgui...@gmail.com 2012-06-25
14:21:54 ---
Thanks for the answer.
Check comment #3 from:
https://bugzilla.kernel.org/show_bug.cgi?id=42921
A similar motherboard Gigabyte GA-990FXA-UD3
(mine is
On 06/25/2012 05:17 PM, Gleb Natapov wrote:
On Mon, Jun 25, 2012 at 04:40:35PM +0300, Avi Kivity wrote:
On 06/25/2012 04:12 PM, Gleb Natapov wrote:
Right. But I think we can have x86_linearize() that doesn't take a
context parameter, only ops.
All ops take context parameter though.
Support the new PV EOI flag in kvm - it just got merged
into kvm.git. Set by default with -cpu kvm.
Set for -cpu qemu by adding +kvm_pv_eoi.
Clear by adding -kvm_pv_eoi to -cpu option.
Signed-off-by: Michael S. Tsirkin m...@redhat.com
---
Note: line is very long but surrounding code seems to
do
On Mon, Jun 25, 2012 at 05:32:31PM +0300, Avi Kivity wrote:
On 06/25/2012 05:17 PM, Gleb Natapov wrote:
On Mon, Jun 25, 2012 at 04:40:35PM +0300, Avi Kivity wrote:
On 06/25/2012 04:12 PM, Gleb Natapov wrote:
Right. But I think we can have x86_linearize() that doesn't take a
context
On 06/25/2012 05:55 PM, Gleb Natapov wrote:
On Mon, Jun 25, 2012 at 05:32:31PM +0300, Avi Kivity wrote:
On 06/25/2012 05:17 PM, Gleb Natapov wrote:
On Mon, Jun 25, 2012 at 04:40:35PM +0300, Avi Kivity wrote:
On 06/25/2012 04:12 PM, Gleb Natapov wrote:
Right. But I think we can have
On Mon, Jun 25, 2012 at 06:03:19PM +0300, Avi Kivity wrote:
On 06/25/2012 05:55 PM, Gleb Natapov wrote:
On Mon, Jun 25, 2012 at 05:32:31PM +0300, Avi Kivity wrote:
On 06/25/2012 05:17 PM, Gleb Natapov wrote:
On Mon, Jun 25, 2012 at 04:40:35PM +0300, Avi Kivity wrote:
On 06/25/2012 04:12
Anyone using these functions has to be prepared that irqchip
support may not be present. It shouldn't be up to the core
code to determine whether this is a fatal error. Currently
code written as:
virq = kvm_irqchip_add_msi_route(...)
if (virq 0) {
slow path
} else {
fast path
}
works
On 06/25/2012 06:35 PM, Gleb Natapov wrote:
Agree. Though the security issue is limited; the structure won't be
uninitialized, it would retain values from the previous call. So it's
limited to intra-guest vulnerabilities.
Yes, that's the kind I mean, not host crash. Intra-guest
On Mon, 2012-06-25 at 01:35 +0300, Michael S. Tsirkin wrote:
On Sun, Jun 24, 2012 at 03:50:12PM -0600, Alex Williamson wrote:
On Sun, 2012-06-24 at 18:40 +0300, Michael S. Tsirkin wrote:
On Sun, Jun 24, 2012 at 08:47:57AM -0600, Alex Williamson wrote:
On Sun, 2012-06-24 at 11:24 +0300,
On Mon, 2012-06-25 at 02:02 +0300, Michael S. Tsirkin wrote:
On Sun, Jun 24, 2012 at 03:59:27PM -0600, Alex Williamson wrote:
On Sun, 2012-06-24 at 18:49 +0300, Michael S. Tsirkin wrote:
On Sun, Jun 24, 2012 at 09:18:38AM -0600, Alex Williamson wrote:
@@ -242,7 +299,8 @@
Hi
Please send in any agenda items you are interested in covering.
jbaron suggested: q35, what are the mergin dependences?
Later, Juan.
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On 6/25/2012 2:16 AM, Jason Wang wrote:
Hello All:
This series is an update version of multiqueue virtio-net driver based on
Krishna Kumar's work to let virtio-net use multiple rx/tx queues to do the
packets reception and transmission. Please review and comments.
Test Environment:
- Intel(R)
Hello Jason,
Good work. Do you have local guest to guest results?
Thanks
Shirley
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On Sun, 2012-06-24 at 09:18 -0600, Alex Williamson wrote:
On Sun, 2012-06-24 at 13:29 +0300, Avi Kivity wrote:
On 06/23/2012 01:16 AM, Alex Williamson wrote:
KVM_IRQFD currently only supports edge triggered interrupts,
asserting then immediately deasserting an interrupt. There are a
On Mon, Jun 25, 2012 at 10:09:37AM -0600, Alex Williamson wrote:
On Mon, 2012-06-25 at 01:35 +0300, Michael S. Tsirkin wrote:
On Sun, Jun 24, 2012 at 03:50:12PM -0600, Alex Williamson wrote:
On Sun, 2012-06-24 at 18:40 +0300, Michael S. Tsirkin wrote:
On Sun, Jun 24, 2012 at 08:47:57AM
On Mon, Jun 25, 2012 at 10:17:14AM -0600, Alex Williamson wrote:
On Mon, 2012-06-25 at 02:02 +0300, Michael S. Tsirkin wrote:
On Sun, Jun 24, 2012 at 03:59:27PM -0600, Alex Williamson wrote:
On Sun, 2012-06-24 at 18:49 +0300, Michael S. Tsirkin wrote:
On Sun, Jun 24, 2012 at 09:18:38AM
Just found another issue:
On Wed, Jun 20, 2012 at 05:33:29PM -0300, Eduardo Habkost wrote:
[...]
@@ -970,27 +974,24 @@ static void numa_add(const char *optarg)
}
node_mem[nodenr] = sval;
}
-if (get_param_value(option, 128, cpus, optarg) == 0) {
On 2012-06-25 17:40, Alex Williamson wrote:
Anyone using these functions has to be prepared that irqchip
support may not be present. It shouldn't be up to the core
code to determine whether this is a fatal error. Currently
code written as:
virq = kvm_irqchip_add_msi_route(...)
if (virq
-Original Message-
From: Eduardo Habkost [mailto:ehabk...@redhat.com]
Sent: Monday, June 25, 2012 1:01 PM
To: Vinod, Chegu
Cc: Hada, Craig M; Hull, Jim; qemu-de...@nongnu.org; kvm@vger.kernel.org
Subject: Re: [Qemu-devel] [PATCH v2] Fixes related to processing of qemu's
-numa option
Hi guys,
Could you guys kindly help me answer these questions below? This is very
helpful for me to learn kvm. Thanks! :-)
Regards,
Zhengwang
Original Message
From: Zhengwang Ruan
Sent: 2012年06月26日 星期二 10时16分49秒
To: kvm
Subject: Some questions from a freshman to this
Hello,
I am freshman to this community, I want to know if there is a mail-list
in which I can ask questions against kvm and people are willing to
answer too? Thanks! :-)
Regards,
Zhengwang
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Hi,
VFIO has been kicking around for well over a year now and has been
posted numerous times for review. The pre-requirements are finally
available in linux-next (or will be in the 20120626 build) so I'd like
to request a new branch be included in linux-next with a goal of being
accepted into
On 06/25/2012 06:14 PM, Michael S. Tsirkin wrote:
On Mon, Jun 25, 2012 at 05:41:17PM +0800, Jason Wang wrote:
Device specific irq optimizations such as irq affinity may be used by virtio
drivers. So this patch introduce a new method to get the irq of a specific
virtqueue.
After this patch,
64-bit host needs to remain in 64-bit mode when an exception take place.
Set interrupt computaion mode in EPCR register.
Signed-off-by: Mihai Caraman mihai.cara...@freescale.com
---
arch/powerpc/kvm/e500mc.c |5 -
1 files changed, 4 insertions(+), 1 deletions(-)
diff --git
Add emulation helper for getting instruction ea and refactor tlb instruction
emulation to use it.
Signed-off-by: Mihai Caraman mihai.cara...@freescale.com
---
arch/powerpc/kvm/e500.h |6 +++---
arch/powerpc/kvm/e500_emulate.c | 21 ++---
arch/powerpc/kvm/e500_tlb.c
Hook DO_KVM macro to 64-bit booke in a optimal way similar to 32-bit booke
see head_fsl_booke.S file. Extend interrupt handlers' parameter list with
interrupt vector numbers to accomodate the macro. Rework Guest Doorbell
handler to use the proper GSRRx save/restore registers.
Only the bolted
Add bookehv interrupt handling support for 64-bit hosts. Change common stack
layout to refer PPC_LR_STKOFF kernel constant. Dispatch the 64-bit execution
flow to the existing kvm_handler_common asm macro. Update input register
values documentation.
Only the bolted version of TLB miss exception
64-bit host runs with lazy interrupt disabling, so local_irq_disable() does
not disable interrupts right away and does not protect against preemption
required by __kvmppc_vcpu_run(). Define a macro for 64-bit to use
hard_irq_disable().
Signed-off-by: Mihai Caraman mihai.cara...@freescale.com
---
Include header file for get_tb() declaration.
Signed-off-by: Mihai Caraman mihai.cara...@freescale.com
---
arch/powerpc/kvm/booke.c |1 +
1 files changed, 1 insertions(+), 0 deletions(-)
diff --git a/arch/powerpc/kvm/booke.c b/arch/powerpc/kvm/booke.c
index db05692..a427031 100644
---
This patchset adds 64-bit Book3E PowerPC support to KVM. It is intended
as a request for comment for scratch register changes and for the support
limited to bolted TLB miss exception handlers.
This work was validated on Freescale's e5500 cores using P5020DS boards.
This patchset is based on Alex
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