On 08/01/2013 10:08 PM, Gleb Natapov wrote:
> From: Nadav Har'El
>
> Some trivial code cleanups not really related to nested EPT.
Reviewed-by: Xiao Guangrong
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On 08/01/2013 07:12 PM, Bharat Bhushan wrote:
"G" bit in MAS2 indicates whether the page is Guarded.
There is no reason to stop guest setting "E", so allow him.
Could we merge patch 2 and 3 into only one.
Tiejun
Signed-off-by: Bharat Bhushan
---
v1->v2
- no change
arch/powerpc/kvm/e5
On 08/01/2013 07:12 PM, Bharat Bhushan wrote:
KVM need to lookup linux pte for getting TLB attributes (WIMGE).
This is similar to how book3s does.
This will be used in follow-up patches.
Signed-off-by: Bharat Bhushan
---
v1->v2
- This is a new change in this version
arch/powerpc/include/as
On 2013-08-02 05:04, Zhang, Yang Z wrote:
> Gleb Natapov wrote on 2013-08-01:
>> From: Nadav Har'El
>>
>> Recent KVM, since
>> http://kerneltrap.org/mailarchive/linux-kvm/2010/5/2/6261577
>> switch the EFER MSR when EPT is used and the host and guest have different
>> NX bits. So if we add support
https://bugzilla.kernel.org/show_bug.cgi?id=60679
Bug ID: 60679
Summary: L2 can't boot up when creating L1 with '-cpu host'
qemu option
Product: Virtualization
Version: unspecified
Kernel Version: 3.11.0-RC1
Hardware: A
On 08/01/2013 10:08 PM, Gleb Natapov wrote:
> From: Nadav Har'El
>
> Some additional comments to preexisting code:
> Explain who (L0 or L1) handles EPT violation and misconfiguration exits.
> Don't mention "shadow on either EPT or shadow" as the only two options.
Reviewed-by: Xiao Guangrong
--
On 31.07.2013 11:20, Gleb Natapov wrote:
> On Wed, Jul 31, 2013 at 11:10:01AM +0200, Stefan Pietsch wrote:
>> On 30.07.2013 07:31, Gleb Natapov wrote:
>>
>>> What happen if you run perf on your host (perf record -a)?
>>> Do you see same NMI messages?
>>
>> It seems that "perf record -a" triggers so
On 08/01/2013 07:12 PM, Bharat Bhushan wrote:
KVM uses same WIM tlb attributes as the corresponding qemu pte.
For this we now search the linux pte for the requested page and
get these cache caching/coherency attributes from pte.
Signed-off-by: Bharat Bhushan
---
v1->v2
- Use Linux pte for wim
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On 08/01/2013 10:08 PM, Gleb Natapov wrote:
> From: Nadav Har'El
>
> KVM's existing shadow MMU code already supports nested TDP. To use it, we
> need to set up a new "MMU context" for nested EPT, and create a few callbacks
> for it (nested_ept_*()). This context should also use the EPT versions o
On 08/01/2013 10:08 PM, Gleb Natapov wrote:
> From: Yang Zhang
>
> Inject nEPT fault to L1 guest. This patch is original from Xinhao.
Reviewed-by: Xiao Guangrong
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We wan't to setup two Oracle instance and make RAC work on them.
Both VM are setup based on libvirt + KVM, we use a lvm lun which
formated in qcow2 format and set the shareable properties in the disk
driver like this:
But when we use it as shared data
On 08/01/2013 10:08 PM, Gleb Natapov wrote:
> need_remote_flush() assumes that shadow page is in PT64 format, but
> with addition of nested EPT this is no longer always true. Fix it by
> bits definitions that depend on host shadow page type.
Reviewed-by: Xiao Guangrong
--
To unsubscribe from thi
On Thu, 2013-08-01 at 16:18 -0600, Alex Williamson wrote:
> vfio-pci needs to support an interface to do hot resets (PCI parent
> bridge secondary bus reset). We need this to support reset of
> co-assigned devices where one or more of the devices does not support
> function level reset. In parti
On 08/01/2013 02:34 PM, Raghavendra K T wrote:
On 08/01/2013 01:15 PM, Gleb Natapov wrote:
Shall I consider this as an ack for kvm part?
For everything except 18/18. For that I still want to see numbers. But
18/18 is pretty independent from the reset of the series so it should
not stop the res
Gleb Natapov wrote on 2013-08-01:
> From: Nadav Har'El
>
> Recent KVM, since
> http://kerneltrap.org/mailarchive/linux-kvm/2010/5/2/6261577
> switch the EFER MSR when EPT is used and the host and guest have different
> NX bits. So if we add support for nested EPT (L1 guest using EPT to run L2)
>
vfio-pci needs to support an interface to do hot resets (PCI parent
bridge secondary bus reset). We need this to support reset of
co-assigned devices where one or more of the devices does not support
function level reset. In particular, discrete graphics cards typically
have no reset options oth
From: David Daney
There are:
.setpush
.setnoreorder
.setnoat
.
.
.
.setpop
Sequences all over the place in this file, but in some places the
final ".set pop" is erroneously converted to ".set push", so none of
these reall
From: David Daney
We need to use more of the Macros in asm.h to allow kvm_locore.S to
build in a 64-bit kernel.
For 32-bit there is no change in the generated object code.
Signed-off-by: David Daney
Acked-by: Ralf Baechle
---
arch/mips/kvm/kvm_locore.S | 54 +++---
From: David Daney
No code changes, just reflowing some comments and consistently using
tabs and spaces. Object code is verified to be unchanged.
Signed-off-by: David Daney
Acked-by: Ralf Baechle
---
arch/mips/kvm/kvm_locore.S | 971 +++--
1 file change
From: David Daney
These shouldn't be too controversial, they just clean things up
without changing the generated code.
More substantial patches will follow, but it seemed like a good idea
to clean this up first.
David Daney (3):
mips/kvm: Improve code formatting in arch/mips/kvm/kvm_locore.S
On 07/31/2013 03:07 PM, Rafael J. Wysocki wrote:
> On Wednesday, July 31, 2013 10:35:05 AM Shuah Khan wrote:
>> On Wed, Jul 31, 2013 at 5:40 AM, Rafael J. Wysocki wrote:
>>> Hi All,
>>>
>>> The original announcement didn't go to linux-pm, so again:
>>>
>>> On Tuesday, July 16, 2013 08:21:26 PM Myr
Some guest paging modes do not support A/D bits. Add support for such
modes in shadow page code. For such modes PT_GUEST_DIRTY_MASK,
PT_GUEST_ACCESSED_MASK, PT_GUEST_DIRTY_SHIFT and PT_GUEST_ACCESSED_SHIFT
should be set to zero.
Reviewed-by: Xiao Guangrong
Signed-off-by: Gleb Natapov
---
arch/x
From: Yang Zhang
Inject nEPT fault to L1 guest. This patch is original from Xinhao.
Signed-off-by: Jun Nakajima
Signed-off-by: Xinhao Xu
Signed-off-by: Yang Zhang
Signed-off-by: Gleb Natapov
---
arch/x86/include/asm/kvm_host.h |4 +++
arch/x86/kvm/mmu.c | 61 +
From: Nadav Har'El
Some trivial code cleanups not really related to nested EPT.
Signed-off-by: Nadav Har'El
Signed-off-by: Jun Nakajima
Signed-off-by: Xinhao Xu
Reviewed-by: Paolo Bonzini
Signed-off-by: Yang Zhang
Signed-off-by: Gleb Natapov
---
arch/x86/kvm/vmx.c |6 ++
1 file ch
need_remote_flush() assumes that shadow page is in PT64 format, but
with addition of nested EPT this is no longer always true. Fix it by
bits definitions that depend on host shadow page type.
Reported-by: Xiao Guangrong
Signed-off-by: Gleb Natapov
---
arch/x86/kvm/mmu.c |8
1 file
Another day -- another version of the nested EPT patches. In this version
included fix for need_remote_flush() with shadowed ept, set bits 6:8
of exit_qualification during ept_violation, update_permission_bitmask()
made to work with shadowed ept pages and other small adjustment according
to review
From: Nadav Har'El
If we let L1 use EPT, we should probably also support the INVEPT instruction.
In our current nested EPT implementation, when L1 changes its EPT table
for L2 (i.e., EPT12), L0 modifies the shadow EPT table (EPT02), and in
the course of this modification already calls INVEPT. Bu
From: Nadav Har'El
Recent KVM, since http://kerneltrap.org/mailarchive/linux-kvm/2010/5/2/6261577
switch the EFER MSR when EPT is used and the host and guest have different
NX bits. So if we add support for nested EPT (L1 guest using EPT to run L2)
and want to be able to run recent KVM as L1, we
This patch makes guest A/D bits definition to be dependable on paging
mode, so when EPT support will be added it will be able to define them
differently.
Reviewed-by: Xiao Guangrong
Signed-off-by: Gleb Natapov
---
arch/x86/kvm/paging_tmpl.h | 30 ++
1 file changed,
From: Nadav Har'El
Some additional comments to preexisting code:
Explain who (L0 or L1) handles EPT violation and misconfiguration exits.
Don't mention "shadow on either EPT or shadow" as the only two options.
Signed-off-by: Nadav Har'El
Signed-off-by: Jun Nakajima
Signed-off-by: Xinhao Xu
Si
From: Nadav Har'El
This is the first patch in a series which adds nested EPT support to KVM's
nested VMX. Nested EPT means emulating EPT for an L1 guest so that L1 can use
EPT when running a nested guest L2. When L1 uses EPT, it allows the L2 guest
to set its own cr3 and take its own page faults
From: Nadav Har'El
The existing code for handling cr3 and related VMCS fields during nested
exit and entry wasn't correct in all cases:
If L2 is allowed to control cr3 (and this is indeed the case in nested EPT),
during nested exit we must copy the modified cr3 from vmcs02 to vmcs12, and
we forg
From: Nadav Har'El
Advertise the support of EPT to the L1 guest, through the appropriate MSR.
This is the last patch of the basic Nested EPT feature, so as to allow
bisection through this patch series: The guest will not see EPT support until
this last patch, and will not attempt to use the half
From: Yang Zhang
Since nEPT doesn't support A/D bit, so we should not set those bit
when build shadow page table.
Reviewed-by: Xiao Guangrong
Signed-off-by: Yang Zhang
Signed-off-by: Gleb Natapov
---
arch/x86/kvm/mmu.c | 12 +---
arch/x86/kvm/paging_tmpl.h |4 ++--
2 fi
From: Nadav Har'El
kvm_set_cr3() attempts to check if the new cr3 is a valid guest physical
address. The problem is that with nested EPT, cr3 is an *L2* physical
address, not an L1 physical address as this test expects.
As the comment above this test explains, it isn't necessary, and doesn't
cor
From: Nadav Har'El
KVM's existing shadow MMU code already supports nested TDP. To use it, we
need to set up a new "MMU context" for nested EPT, and create a few callbacks
for it (nested_ept_*()). This context should also use the EPT versions of
the page table access functions (defined in the prev
From: Nadav Har'El
For preparation, we just move gpte_access(), prefetch_invalid_gpte(),
s_rsvd_bits_set(), protect_clean_gpte() and is_dirty_gpte() from mmu.c
to paging_tmpl.h.
Reviewed-by: Xiao Guangrong
Signed-off-by: Nadav Har'El
Signed-off-by: Jun Nakajima
Signed-off-by: Xinhao Xu
Signe
On Thu, Aug 01, 2013 at 03:13:02PM +0200, Paolo Bonzini wrote:
> > > > > > > Not sure this explicit "inline" is needed... Gcc always inlines
> > > > > > > the small and
> > > > > > > static functions.
> > > > > >
> > > > > > Paolo asked for it, but now I see that I did in in a wrong patch. I
> >
> > > > > > Not sure this explicit "inline" is needed... Gcc always inlines the
> > > > > > small and
> > > > > > static functions.
> > > > >
> > > > > Paolo asked for it, but now I see that I did in in a wrong patch. I do
> > > > > not care much personally either way, I agree with you though, co
On Thu, Aug 01, 2013 at 02:03:01PM +0200, Paolo Bonzini wrote:
> On Aug 01 2013, Gleb Natapov wrote:
> > On Thu, Aug 01, 2013 at 01:19:11PM +0200, Paolo Bonzini wrote:
> > > On Aug 01 2013, Gleb Natapov wrote:
> > > > On Thu, Aug 01, 2013 at 04:31:31PM +0800, Xiao Guangrong wrote:
> > > > > On 07
On 07/31/2013 05:48 PM, Gleb Natapov wrote:
> From: Nadav Har'El
>
> kvm_set_cr3() attempts to check if the new cr3 is a valid guest physical
> address. The problem is that with nested EPT, cr3 is an *L2* physical
> address, not an L1 physical address as this test expects.
>
> As the comment abo
On Aug 01 2013, Gleb Natapov wrote:
> On Thu, Aug 01, 2013 at 01:19:11PM +0200, Paolo Bonzini wrote:
> > On Aug 01 2013, Gleb Natapov wrote:
> > > On Thu, Aug 01, 2013 at 04:31:31PM +0800, Xiao Guangrong wrote:
> > > > On 07/31/2013 10:48 PM, Gleb Natapov wrote:
> > > > > From: Yang Zhang
> > >
On Thu, Aug 01, 2013 at 01:19:11PM +0200, Paolo Bonzini wrote:
> On Aug 01 2013, Gleb Natapov wrote:
> > On Thu, Aug 01, 2013 at 04:31:31PM +0800, Xiao Guangrong wrote:
> > > On 07/31/2013 10:48 PM, Gleb Natapov wrote:
> > > > From: Yang Zhang
> > > >
> > > > Inject nEPT fault to L1 guest. This
On 07/31/2013 05:48 PM, Gleb Natapov wrote:
> From: Nadav Har'El
>
> The existing code for handling cr3 and related VMCS fields during nested
> exit and entry wasn't correct in all cases:
>
> If L2 is allowed to control cr3 (and this is indeed the case in nested EPT),
> during nested exit we mus
On 07/31/2013 05:48 PM, Gleb Natapov wrote:
> From: Nadav Har'El
>
> Recent KVM, since http://kerneltrap.org/mailarchive/linux-kvm/2010/5/2/6261577
> switch the EFER MSR when EPT is used and the host and guest have different
> NX bits. So if we add support for nested EPT (L1 guest using EPT to ru
On Aug 01 2013, Gleb Natapov wrote:
> On Thu, Aug 01, 2013 at 04:31:31PM +0800, Xiao Guangrong wrote:
> > On 07/31/2013 10:48 PM, Gleb Natapov wrote:
> > > From: Yang Zhang
> > >
> > > Inject nEPT fault to L1 guest. This patch is original from Xinhao.
> > >
> > > Signed-off-by: Jun Nakajima
>
KVM uses same WIM tlb attributes as the corresponding qemu pte.
For this we now search the linux pte for the requested page and
get these cache caching/coherency attributes from pte.
Signed-off-by: Bharat Bhushan
---
v1->v2
- Use Linux pte for wimge rather than RAM/no-RAM mechanism
arch/powerp
KVM need to lookup linux pte for getting TLB attributes (WIMGE).
This is similar to how book3s does.
This will be used in follow-up patches.
Signed-off-by: Bharat Bhushan
---
v1->v2
- This is a new change in this version
arch/powerpc/include/asm/kvm_booke.h | 73 +
Linux pte search functions find_linux_pte_or_hugepte() and
find_linux_pte() have nothing specific to 64bit anymore.
So they are move from pgtable-ppc64.h to asm/pgtable.h
Signed-off-by: Bharat Bhushan
---
v1->v2
- This is a new change in this version
arch/powerpc/include/asm/pgtable-ppc64.h |
From: Bharat Bhushan
First patch is a typo fix where book3e define _PAGE_LENDIAN while it should be
defined as _PAGE_ENDIAN. This seems to show that this is never exercised :-)
Second and third patch is to allow guest controlling "G"-Guarded and
"E"-Endiany TLB attributes respectively.
Rest of
"G" bit in MAS2 indicates whether the page is Guarded.
There is no reason to stop guest setting "E", so allow him.
Signed-off-by: Bharat Bhushan
---
v1->v2
- no change
arch/powerpc/kvm/e500.h |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/arch/powerpc/kvm/e500.h b/a
"E" bit in MAS2 bit indicates whether the page is accessed
in Little-Endian or Big-Endian byte order.
There is no reason to stop guest setting "E", so allow him."
Signed-off-by: Bharat Bhushan
---
v1->v2
- no change
arch/powerpc/kvm/e500.h |2 +-
1 files changed, 1 insertions(+), 1 deleti
For booke3e _PAGE_ENDIAN is not defined. Infact what is defined
is "_PAGE_LENDIAN" which is wrong and should be _PAGE_ENDIAN.
There are no compilation errors as
arch/powerpc/include/asm/pte-common.h defines _PAGE_ENDIAN to 0
as it is not defined anywhere.
Signed-off-by: Bharat Bhushan
---
v1->v2
On Thu, Aug 01, 2013 at 01:05:47PM +0200, Paolo Bonzini wrote:
> On Aug 01 2013, Xiao Guangrong wrote:
> > On 08/01/2013 03:42 PM, Gleb Natapov wrote:
> > > On Thu, Aug 01, 2013 at 03:31:01PM +0800, Xiao Guangrong wrote:
> > >> On 08/01/2013 03:18 PM, Xiao Guangrong wrote:
> > >> +#endif
> >
On Aug 01 2013, Xiao Guangrong wrote:
> On 08/01/2013 03:42 PM, Gleb Natapov wrote:
> > On Thu, Aug 01, 2013 at 03:31:01PM +0800, Xiao Guangrong wrote:
> >> On 08/01/2013 03:18 PM, Xiao Guangrong wrote:
> >> +#endif
> >
> > Hmm, why not use shadow_x_mask, shadow_user_mask instead?
>
On 08/01/2013 05:16 PM, Xiao Guangrong wrote:
> On 07/31/2013 10:48 PM, Gleb Natapov wrote:
>> From: Nadav Har'El
>>
>> KVM's existing shadow MMU code already supports nested TDP. To use it, we
>> need to set up a new "MMU context" for nested EPT, and create a few callbacks
>> for it (nested_ept_*
On Thu, Aug 01, 2013 at 05:16:07PM +0800, Xiao Guangrong wrote:
> On 07/31/2013 10:48 PM, Gleb Natapov wrote:
> > From: Nadav Har'El
> >
> > KVM's existing shadow MMU code already supports nested TDP. To use it, we
> > need to set up a new "MMU context" for nested EPT, and create a few
> > callb
On 07/31/2013 10:48 PM, Gleb Natapov wrote:
> From: Nadav Har'El
>
> KVM's existing shadow MMU code already supports nested TDP. To use it, we
> need to set up a new "MMU context" for nested EPT, and create a few callbacks
> for it (nested_ept_*()). This context should also use the EPT versions o
On 08/01/2013 01:15 PM, Gleb Natapov wrote:
On Thu, Aug 01, 2013 at 01:08:47PM +0530, Raghavendra K T wrote:
On 07/31/2013 11:54 AM, Gleb Natapov wrote:
On Tue, Jul 30, 2013 at 10:13:12PM +0530, Raghavendra K T wrote:
On 07/25/2013 03:08 PM, Raghavendra K T wrote:
On 07/25/2013 02:45 PM, Gleb
On Thu, Aug 01, 2013 at 04:31:31PM +0800, Xiao Guangrong wrote:
> On 07/31/2013 10:48 PM, Gleb Natapov wrote:
> > From: Yang Zhang
> >
> > Inject nEPT fault to L1 guest. This patch is original from Xinhao.
> >
> > Signed-off-by: Jun Nakajima
> > Signed-off-by: Xinhao Xu
> > Signed-off-by: Yang
On 07/31/2013 10:48 PM, Gleb Natapov wrote:
> From: Yang Zhang
>
> Inject nEPT fault to L1 guest. This patch is original from Xinhao.
>
> Signed-off-by: Jun Nakajima
> Signed-off-by: Xinhao Xu
> Signed-off-by: Yang Zhang
> Signed-off-by: Gleb Natapov
> ---
> arch/x86/include/asm/kvm_host.h
> vscsi->num_queues counts the number of request virtqueue which does not
> include the control and event virtqueue. It is wrong to subtract
> VIRTIO_SCSI_VQ_BASE from vscsi->num_queues.
Reviewed-by: Paolo Bonzini
> This patch fixes the following panic.
>
> (qemu) device_del scsi0
>
> BUG: un
On Thu, Aug 01, 2013 at 03:51:35PM +0800, Xiao Guangrong wrote:
> On 08/01/2013 03:42 PM, Gleb Natapov wrote:
> > On Thu, Aug 01, 2013 at 03:31:01PM +0800, Xiao Guangrong wrote:
> >> On 08/01/2013 03:18 PM, Xiao Guangrong wrote:
> >> +#endif
> >
> > Hmm, why not use shadow_x_mask, shadow_u
On 08/01/2013 03:42 PM, Gleb Natapov wrote:
> On Thu, Aug 01, 2013 at 03:31:01PM +0800, Xiao Guangrong wrote:
>> On 08/01/2013 03:18 PM, Xiao Guangrong wrote:
>> +#endif
>
> Hmm, why not use shadow_x_mask, shadow_user_mask instead? PT_WRITABLE_MASK
> is also suitable for ept, i guess w
On Thu, Aug 01, 2013 at 01:08:47PM +0530, Raghavendra K T wrote:
> On 07/31/2013 11:54 AM, Gleb Natapov wrote:
> >On Tue, Jul 30, 2013 at 10:13:12PM +0530, Raghavendra K T wrote:
> >>On 07/25/2013 03:08 PM, Raghavendra K T wrote:
> >>>On 07/25/2013 02:45 PM, Gleb Natapov wrote:
> On Thu, Jul 25
On Thu, Aug 01, 2013 at 03:31:01PM +0800, Xiao Guangrong wrote:
> On 08/01/2013 03:18 PM, Xiao Guangrong wrote:
> +#endif
> >>>
> >>> Hmm, why not use shadow_x_mask, shadow_user_mask instead? PT_WRITABLE_MASK
> >>> is also suitable for ept, i guess we can remove the "#if/#else/#endif"
> >>> after
On 07/31/2013 11:54 AM, Gleb Natapov wrote:
On Tue, Jul 30, 2013 at 10:13:12PM +0530, Raghavendra K T wrote:
On 07/25/2013 03:08 PM, Raghavendra K T wrote:
On 07/25/2013 02:45 PM, Gleb Natapov wrote:
On Thu, Jul 25, 2013 at 02:47:37PM +0530, Raghavendra K T wrote:
On 07/24/2013 06:06 PM, Ragh
On 08/01/2013 03:18 PM, Xiao Guangrong wrote:
+#endif
>>>
>>> Hmm, why not use shadow_x_mask, shadow_user_mask instead? PT_WRITABLE_MASK
>>> is also suitable for ept, i guess we can remove the "#if/#else/#endif" after
>>> that.
>>>
>> shadow_x_mask and shadow_user_mask do not depend on guest pagin
On Thu, Aug 01, 2013 at 03:24:06PM +0800, Xiao Guangrong wrote:
> On 07/31/2013 10:48 PM, Gleb Natapov wrote:
> > From: Yang Zhang
>
> > }
> > }
> > return emulate;
> > diff --git a/arch/x86/kvm/paging_tmpl.h b/arch/x86/kvm/paging_tmpl.h
> > index 762c904..0d25351 100644
> > -
On 07/31/2013 10:48 PM, Gleb Natapov wrote:
> From: Yang Zhang
> }
> }
> return emulate;
> diff --git a/arch/x86/kvm/paging_tmpl.h b/arch/x86/kvm/paging_tmpl.h
> index 762c904..0d25351 100644
> --- a/arch/x86/kvm/paging_tmpl.h
> +++ b/arch/x86/kvm/paging_tmpl.h
> @@ -555
On 08/01/2013 03:10 PM, Gleb Natapov wrote:
> On Thu, Aug 01, 2013 at 03:00:12PM +0800, Xiao Guangrong wrote:
>> On 07/31/2013 10:48 PM, Gleb Natapov wrote:
>>> From: Nadav Har'El
>>>
>>> This is the first patch in a series which adds nested EPT support to KVM's
>>> nested VMX. Nested EPT means em
On Thu, Aug 01, 2013 at 03:00:12PM +0800, Xiao Guangrong wrote:
> On 07/31/2013 10:48 PM, Gleb Natapov wrote:
> > From: Nadav Har'El
> >
> > This is the first patch in a series which adds nested EPT support to KVM's
> > nested VMX. Nested EPT means emulating EPT for an L1 guest so that L1 can
>
On 07/31/2013 10:48 PM, Gleb Natapov wrote:
> From: Nadav Har'El
>
> This is the first patch in a series which adds nested EPT support to KVM's
> nested VMX. Nested EPT means emulating EPT for an L1 guest so that L1 can use
> EPT when running a nested guest L2. When L1 uses EPT, it allows the L2
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