Hi Alex,
On Wed, Jan 22, 2014 at 12:11 PM, Alexander Graf ag...@suse.de wrote:
Am 22.01.2014 um 07:31 schrieb Anup Patel a...@brainfault.org:
On Wed, Jan 22, 2014 at 11:09 AM, Victor Kamensky
victor.kamen...@linaro.org wrote:
Hi Guys,
Christoffer and I had a bit heated chat :) on this
On 22 January 2014 05:39, Victor Kamensky victor.kamen...@linaro.org wrote:
Hi Guys,
Christoffer and I had a bit heated chat :) on this
subject last night. Christoffer, really appreciate
your time! We did not really reach agreement
during the chat and Christoffer asked me to follow
up on
Il 21/01/2014 19:59, Liu, Jinsong ha scritto:
From 3155a190ce6ebb213e6c724240f4e6620ba67a9d Mon Sep 17 00:00:00 2001
From: Liu Jinsong jinsong@intel.com
Date: Fri, 13 Dec 2013 02:32:03 +0800
Subject: [PATCH v3 1/4] KVM/X86: Fix xsave cpuid exposing bug
EBX of cpuid(0xD, 0) is dynamic per
On 01/22/2014 02:21 AM, Paolo Bonzini wrote:
Il 21/01/2014 19:59, Liu, Jinsong ha scritto:
From 3155a190ce6ebb213e6c724240f4e6620ba67a9d Mon Sep 17 00:00:00 2001
From: Liu Jinsong jinsong@intel.com
Date: Fri, 13 Dec 2013 02:32:03 +0800
Subject: [PATCH v3 1/4] KVM/X86: Fix xsave cpuid
On 22.01.2014, at 08:26, Victor Kamensky victor.kamen...@linaro.org wrote:
On 21 January 2014 22:41, Alexander Graf ag...@suse.de wrote:
Native endian really is just a shortcut for target endian
which is LE for ARM and BE for PPC. There shouldn't be
a qemu-system-armeb or
Il 21/01/2014 19:59, Liu, Jinsong ha scritto:
From 3155a190ce6ebb213e6c724240f4e6620ba67a9d Mon Sep 17 00:00:00 2001
From: Liu Jinsong jinsong@intel.com
Date: Fri, 13 Dec 2013 02:32:03 +0800
Subject: [PATCH v3 1/4] KVM/X86: Fix xsave cpuid exposing bug
EBX of cpuid(0xD, 0) is dynamic per
Il 21/01/2014 20:01, Liu, Jinsong ha scritto:
From 31e68d752ac395dc6b65e6adf45be5324e92cdc8 Mon Sep 17 00:00:00 2001
From: Liu Jinsong jinsong@intel.com
Date: Fri, 13 Dec 2013 02:32:43 +0800
Subject: [PATCH v3 2/4] KVM/X86: Intel MPX vmx and msr handle
This patch handle vmx and msr of Intel
Il 22/01/2014 12:38, Paolo Bonzini ha scritto:
Il 21/01/2014 20:01, Liu, Jinsong ha scritto:
From 31e68d752ac395dc6b65e6adf45be5324e92cdc8 Mon Sep 17 00:00:00 2001
From: Liu Jinsong jinsong@intel.com
Date: Fri, 13 Dec 2013 02:32:43 +0800
Subject: [PATCH v3 2/4] KVM/X86: Intel MPX vmx and
Il 22/01/2014 06:29, Liu, Jinsong ha scritto:
These patches are version 3 to enalbe Intel MPX for KVM.
Version 1:
* Add some Intel MPX definiation
* Fix a cpuid(0x0d, 0) exposing bug, dynamic per XCR0 features enable/disable
* vmx and msr handle for MPX support at KVM
* enalbe MPX
On Wed, Jan 22, 2014 at 04:27:45PM +0800, Michael wang wrote:
# CONFIG_PREEMPT_NONE is not set
CONFIG_PREEMPT_VOLUNTARY=y
# CONFIG_PREEMPT is not set
Could you try the patch here:
lkml.kernel.org/r/20140122102435.gh31...@twins.programming.kicks-ass.net
I suspect its the same issue.
--
To
Il 21/01/2014 18:11, Radim Krčmář ha scritto:
KVM introduced internal error exit reason and suberror at the same time,
and later extended it with internal error data.
QEMU does not report suberror on hosts between these two events because
we check for the extension. (half a year in 2009, but it
Il 22/01/2014 13:36, Peter Zijlstra ha scritto:
On Wed, Jan 22, 2014 at 04:27:45PM +0800, Michael wang wrote:
# CONFIG_PREEMPT_NONE is not set
CONFIG_PREEMPT_VOLUNTARY=y
# CONFIG_PREEMPT is not set
Could you try the patch here:
Linus,
The following changes since commit dc1ccc48159d63eca5089e507c82c7d22ef60839:
Linux 3.13-rc2 (2013-11-29 12:57:14 -0800)
are available in the git repository at:
git://git.kernel.org/pub/scm/virt/kvm/kvm.git tags/for-linus
for you to fetch changes up to
When the guest runs with caches disabled (like in an early boot
sequence, for example), all the writes are diectly going to RAM,
bypassing the caches altogether.
Once the MMU and caches are enabled, whatever sits in the cache
becomes suddently visible, which isn't what the guest expects.
A way
When we run a guest with cache disabled, we don't flush the cache to
the Point of Coherency, hence possibly missing bits of data that have
been written in the cache, but have not yet reached memory.
We also have the opposite issue: when a guest enables its cache,
whatever sits in the cache is
The current handling of AArch32 trapping is slightly less than
perfect, as it is not possible (from a handler point of view)
to distinguish it from an AArch64 access, nor to tell a 32bit
from a 64bit access either.
Fix this by introducing two additional flags:
- is_aarch32: true if the access was
In order for the guest with caches off to observe data written
contained in a given page, we need to make sure that page is
committed to memory, and not just hanging in the cache (as
guest accesses are completely bypassing the cache until it
decides to enable it).
For this purpose, hook into the
Commit 240e99cbd00a (ARM: KVM: Fix 64-bit coprocessor handling)
added an ordering dependency for the 64bit registers.
The order described is: CRn, CRm, Op1, Op2, 64bit-first.
Unfortunately, the implementation is: CRn, 64bit-first, CRm...
Move the 64bit test to be last in order to match the
In order to be able to detect the point where the guest enables
its MMU and caches, trap all the VM related system registers.
Once we see the guest enabling both the MMU and the caches, we
can go back to a saner mode of operation, which is to leave these
registers in complete control of the
Commit 240e99cbd00a (ARM: KVM: Fix 64-bit coprocessor handling)
changed the way we match the 64bit coprocessor access from
user space, but didn't update the trap handler for the same
set of registers.
The effect is that a trapped 64bit access is never matched, leading
to a fault being injected
In order to be able to detect the point where the guest enables
its MMU and caches, trap all the VM related system registers.
Once we see the guest enabling both the MMU and the caches, we
can go back to a saner mode of operation, which is to leave these
registers in complete control of the
HCR.TVM traps (among other things) accesses to AMAIR0 and AMAIR1.
In order to minimise the amount of surprise a guest could generate by
trying to access these registers with caches off, add them to the
list of registers we switch/handle.
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
In order for the guest with caches off to observe data written
contained in a given page, we need to make sure that page is
committed to memory, and not just hanging in the cache (as
guest accesses are completely bypassing the cache until it
decides to enable it).
For this purpose, hook into the
So far, KVM/ARM used a fixed HCR configuration per guest, except for
the VI/VF/VA bits to control the interrupt in absence of VGIC.
With the upcoming need to dynamically reconfigure trapping, it becomes
necessary to allow the HCR to be changed on a per-vcpu basis.
The fix here is to mimic what
Il 04/01/2014 18:59, Jan Kiszka ha scritto:
From: Jan Kiszka jan.kis...@siemens.com
Some compiler versions (seen with gcc 4.8.1) move the resume label after
the return statement which, of course, causes sever problems.
Can you include the assembly output? Do you mean after the ret
On Tue, Jan 21, 2014 at 04:06:05PM -0200, Alejandro Comisario wrote:
CCed Michael Tsirkin and Jason Wang who work on KVM networking.
Hi guys, we had in the past when using physical servers, several
throughput issues regarding the throughput of our APIS, in our case we
measure this with
On Mon, Jan 20, 2014 at 02:25:36PM +0100, Paolo Bonzini wrote:
The original patch from Liu Jinsong restricted them to reset or full
state updates, but that's unnecessary (and wrong) since the BNDCFGS
MSR has no side effects.
Why is it necessary to save/restore BNDCFGS MSR on states other
than
On Tue, Jan 21, 2014 at 11:23:37PM +0900, Fernando Luis Vazquez Cao wrote:
(2014/01/21 9:19), Marcelo Tosatti wrote:
On Mon, Jan 20, 2014 at 11:59:39PM +0900, Fernando Luis Vazquez Cao wrote:
(2014/01/20 22:33), Marcelo Tosatti wrote:
On Mon, Jan 20, 2014 at 11:56:56AM +0200, Nadav Har'El
Il 22/01/2014 16:29, Marcelo Tosatti ha scritto:
The original patch from Liu Jinsong restricted them to reset or full
state updates, but that's unnecessary (and wrong) since the BNDCFGS
MSR has no side effects.
Why is it necessary to save/restore BNDCFGS MSR on states other
than FULL and
Il 22/01/2014 16:00, Paolo Bonzini ha scritto:
Il 04/01/2014 18:59, Jan Kiszka ha scritto:
From: Jan Kiszka jan.kis...@siemens.com
Some compiler versions (seen with gcc 4.8.1) move the resume label after
the return statement which, of course, causes sever problems.
Can you include the
After KVM commit 8a3caa6d74597c2a083f7c87f866891a0b12540b, kvm-kmod
is broken in weird ways (for me it breaks every other time kvm is
loaded, but only with ept=0...).
The reason is that, after this commit, empty_zero_page is expected
to be page-aligned, but the kvm-kmod compatibility shim isn't.
Hi Peter,
On 22 January 2014 02:22, Peter Maydell peter.mayd...@linaro.org wrote:
On 22 January 2014 05:39, Victor Kamensky victor.kamen...@linaro.org wrote:
Hi Guys,
Christoffer and I had a bit heated chat :) on this
subject last night. Christoffer, really appreciate
your time! We did not
Il 04/01/2014 18:59, Jan Kiszka ha scritto:
Highlights:
- improved preemption timer and interrupt injection tests
(obsoletes my two patches in vmx queue)
- tests for IA32_APIC_BASE writes
- test for unconditional IO exiting (VMX)
- basic test of debug facilities (hw breakpoints etc.)
Jan
On 22 January 2014 17:19, Victor Kamensky victor.kamen...@linaro.org wrote:
On 22 January 2014 02:22, Peter Maydell peter.mayd...@linaro.org wrote:
but the major issue here is that the data being
transferred is not just a bag of bytes. The data[]
array plus the size field are being (mis)used
On 22 January 2014 09:29, Peter Maydell peter.mayd...@linaro.org wrote:
On 22 January 2014 17:19, Victor Kamensky victor.kamen...@linaro.org wrote:
On 22 January 2014 02:22, Peter Maydell peter.mayd...@linaro.org wrote:
but the major issue here is that the data being
transferred is not just a
On 22 January 2014 19:29, Victor Kamensky victor.kamen...@linaro.org wrote:
On 22 January 2014 09:29, Peter Maydell peter.mayd...@linaro.org wrote:
This just isn't how real buses work. There is no
address + 1, address + 2. There is a single address
for the memory transaction and a set of data
Thank you so much Stefan for the help and cc'ing Michael Jason.
Like you advised yesterday on IRC, today we are making some tests with
the application setting TCP_NODELAY in the socket options.
So we will try that and get back to you with further information.
In the mean time, maybe showing what
On 22 January 2014 12:02, Peter Maydell peter.mayd...@linaro.org wrote:
On 22 January 2014 19:29, Victor Kamensky victor.kamen...@linaro.org wrote:
On 22 January 2014 09:29, Peter Maydell peter.mayd...@linaro.org wrote:
This just isn't how real buses work. There is no
address + 1, address + 2.
On 22 January 2014 22:47, Victor Kamensky victor.kamen...@linaro.org wrote:
You deleted my example, but I need it again:
Consider the following ARM code snippets:
setend le
mov r1, #0x04030201
str r1, [r0]
and
setend be
mov r1, #0x01020304
str r1, [r0]
Just for LE host case basically
Peter, could I please ask you a favor. Could you please
stop deleting pieces of your and my previous responses
when you reply.
Please just reply inline. Sometimes I would like to
reference my or your previous statement, but I could not
find it in your response email. It is very bizzar. Sorry,
it
[Re: [PATCH RFC 00/73] tree-wide: clean up some no longer required #include
linux/init.h] On 22/01/2014 (Wed 18:00) Stephen Rothwell wrote:
Hi Paul,
On Tue, 21 Jan 2014 16:22:03 -0500 Paul Gortmaker
paul.gortma...@windriver.com wrote:
Where: This work exists as a queue of patches that
On 01/22/2014 08:36 PM, Peter Zijlstra wrote:
On Wed, Jan 22, 2014 at 04:27:45PM +0800, Michael wang wrote:
# CONFIG_PREEMPT_NONE is not set
CONFIG_PREEMPT_VOLUNTARY=y
# CONFIG_PREEMPT is not set
Could you try the patch here:
On 01/22/2014 11:22 PM, Stefan Hajnoczi wrote:
On Tue, Jan 21, 2014 at 04:06:05PM -0200, Alejandro Comisario wrote:
CCed Michael Tsirkin and Jason Wang who work on KVM networking.
Hi guys, we had in the past when using physical servers, several
throughput issues regarding the throughput of
On 01/23/2014 05:32 AM, Alejandro Comisario wrote:
Thank you so much Stefan for the help and cc'ing Michael Jason.
Like you advised yesterday on IRC, today we are making some tests with
the application setting TCP_NODELAY in the socket options.
So we will try that and get back to you with
Hi Alex,
Sorry, for delayed reply, I was focusing on discussion
with Peter. Hope you and other folks may get something
out of it :).
Please see responses inline
On 22 January 2014 02:52, Alexander Graf ag...@suse.de wrote:
On 22.01.2014, at 08:26, Victor Kamensky victor.kamen...@linaro.org
Vadim Rozenfeld (2):
mark hyper-v hypercall page as dirty
mark hyper-v vapic assist page as dirty
arch/x86/kvm/x86.c | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
--
1.8.1.4
--
To unsubscribe from this list: send the line unsubscribe kvm in
the body of a message to
Signed-off-by: Vadim Rozenfeld vroze...@redhat.com
---
arch/x86/kvm/x86.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c
index e8599ed..cd8a41f 100644
--- a/arch/x86/kvm/x86.c
+++ b/arch/x86/kvm/x86.c
@@ -1869,19 +1869,21 @@
Signed-off-by: Vadim Rozenfeld vroze...@redhat.com
---
arch/x86/kvm/x86.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c
index 59b95b1..e8599ed 100644
--- a/arch/x86/kvm/x86.c
+++ b/arch/x86/kvm/x86.c
@@ -1840,6 +1840,7 @@ static int
48 matches
Mail list logo
