This patch make sure we inherit the LE bit correctly in different case
so that we can run Little Endian distro in PR mode
Signed-off-by: Aneesh Kumar K.V
---
Changes from V2:
* Move H_SET_MODE to qemu
arch/powerpc/include/asm/kvm_host.h | 1 +
arch/powerpc/kernel/asm-offsets.c | 1 +
arch
Although it's optional IBM POWER cpus always had DAR value set on
alignment interrupt. So don't try to compute these values.
Signed-off-by: Aneesh Kumar K.V
---
Changes from V2:
* Depend on cpu feature flag to decide whether to use fault_dsir or not
arch/powerpc/include/asm/cputable.h| 1 +
On Mon, 2014-01-27 at 16:44 -0800, Christoffer Dall wrote:
> I'm loosing track of this discussion, Ben, can you explain a bit? You
> wrote:
>
> Having a byte array coming in that represents what the CPU does in its
> current byte order means you do *NOT* need to query the endianness of
> t
On Wed, 2014-01-22 at 19:38 -0500, Paul Gortmaker wrote:
> Thanks, it was a great help as it uncovered a few issues in fringe arch
> that I didn't have toolchains for, and I've fixed all of those up.
>
> I've noticed that powerpc has been un-buildable for a while now; I have
> used this hack patc
On Sat, 2014-01-25 at 03:15 +0100, Alexander Graf wrote:
> Ok, let's go through the combinations for a 32-bit write of 0x01020304 on PPC
> and what data[] looks like
>
> your proposal:
>
> BE guest, BE host: { 0x01, 0x02, 0x03, 0x04 }
> LE guest, BE host: { 0x04, 0x03, 0x02, 0x01 }
> BE gu
On Tue, Jan 28, 2014 at 11:36:13AM +1100, Benjamin Herrenschmidt wrote:
> On Mon, 2014-01-27 at 23:49 +, Peter Maydell wrote:
> >
> > Er, what? If we make the array be guest's current order
> > then by definition userspace has to look at the guest's
> > current endianness. I agree that would b
On Tue, Jan 28, 2014 at 11:32:41AM +1100, Benjamin Herrenschmidt wrote:
> On Thu, 2014-01-23 at 20:11 -0800, Victor Kamensky wrote:
> > > I would take 50 byteswaps with a clear ABI any day over an obscure
> > > standard that can avoid a single hardware-on-register instruction.
> > This
> > > is abo
On Mon, 2014-01-27 at 23:49 +, Peter Maydell wrote:
>
> Er, what? If we make the array be guest's current order
> then by definition userspace has to look at the guest's
> current endianness. I agree that would be bad. Either
> of the two current proposals (host kernel order; guest
> CPU's nat
On Thu, 2014-01-23 at 20:11 -0800, Victor Kamensky wrote:
> > I would take 50 byteswaps with a clear ABI any day over an obscure
> > standard that can avoid a single hardware-on-register instruction.
> This
> > is about designing a clean software interface, not about building an
> > optimized integ
> The point is simple, and Peter has made it over and over:
> Any consumer of a memory operation sees "value, len, address".
>
> This is what KVM_EXIT_MMIO emulates. So just by knowing the ABI
> definition and having a pointer to the structure you need to be able to
> tell me "value, len, addres
On Thu, 2014-01-23 at 15:33 +, Peter Maydell wrote:
> (4) PPC CPUs in BE mode and ARM CPUs in BE mode are not
> the same, because in the ARM case it is doing an
> internal-to-CPU byteswap, and in the PPC case it is not
Aren't they both byte-order invariant ?
In that case they are t
On Tue, 2014-01-28 at 11:07 +1100, Benjamin Herrenschmidt wrote:
> On Thu, 2014-01-23 at 15:33 +, Peter Maydell wrote:
> > (4) PPC CPUs in BE mode and ARM CPUs in BE mode are not
> > the same, because in the ARM case it is doing an
> > internal-to-CPU byteswap, and in the PPC case it
On 27 January 2014 23:34, Benjamin Herrenschmidt
wrote:
> On Wed, 2014-01-22 at 20:02 +, Peter Maydell wrote:
>>
>> Defining it as being always guest-order would mean that
>> userspace had to continually look at the guest CPU
>> endianness bit, which is annoying and awkward.
>>
>> Defining it
On Wed, 2014-01-22 at 20:02 +, Peter Maydell wrote:
>
> Defining it as being always guest-order would mean that
> userspace had to continually look at the guest CPU
> endianness bit, which is annoying and awkward.
>
> Defining it as always host-endian order is the most
> reasonable option ava
On Wed, 2014-01-22 at 11:29 -0800, Victor Kamensky wrote:
> I don't see why you so attached to desire to describe
> data part of memory transaction as just one of int
> types. If we are talking about bunch of hypothetical
> cases imagine such bus that allow transaction with
> size of 6 bytes. How d
On Wed, 2014-01-22 at 17:29 +, Peter Maydell wrote:
>
> > Basically if it would be on real bus, get byte value
> > that corresponds to phys_addr + 0 address place
> > it into data[0], get byte value that corresponds to
> > phys_addr + 1 address place it into data[1], etc.
>
> This just isn't
Il 17/01/2014 10:41, Jan Beulich ha scritto:
> One half of this doesn't apply here, due to the explicit barriers
> that are there. The half about converting local variable accesses
> back to memory reads (i.e. eliding the local variable), however,
> is only a theoretical issue afaict: If a compiler
On Mon, Jan 27, 2014 at 05:02:25PM +, Marc Zyngier wrote:
> On 27/01/14 16:57, Catalin Marinas wrote:
> > On Mon, Jan 27, 2014 at 11:16:57AM +, Marc Zyngier wrote:
> >> On 24/01/14 23:37, Christoffer Dall wrote:
> >>> On Sat, Jan 04, 2014 at 08:27:23AM -0800, Christoffer Dall wrote:
>
On 27/01/14 16:57, Catalin Marinas wrote:
> On Mon, Jan 27, 2014 at 11:16:57AM +, Marc Zyngier wrote:
>> On 24/01/14 23:37, Christoffer Dall wrote:
>>> On Sat, Jan 04, 2014 at 08:27:23AM -0800, Christoffer Dall wrote:
--- a/arch/arm/include/asm/pgtable-3level.h
+++ b/arch/arm/include/
On Mon, Jan 27, 2014 at 11:16:57AM +, Marc Zyngier wrote:
> On 24/01/14 23:37, Christoffer Dall wrote:
> > On Sat, Jan 04, 2014 at 08:27:23AM -0800, Christoffer Dall wrote:
> >> --- a/arch/arm/include/asm/pgtable-3level.h
> >> +++ b/arch/arm/include/asm/pgtable-3level.h
> >> @@ -120,13 +120,19
Alexander Graf writes:
> On 27.01.2014, at 11:28, Aneesh Kumar K.V
> wrote:
>
>> Alexander Graf writes:
>>
>>> On 21.01.2014, at 10:42, Aneesh Kumar K.V
>>> wrote:
>>>
Liu Ping Fan writes:
> To make sure that on host, the pages marked with _PAGE_NUMA result in a
> faul
On 08.01.2014, at 11:25, Paul Mackerras wrote:
> This series of patches adds support for the new POWER8 processor in
> HV-mode KVM. The series is based on a merge of Alex Graf's for-3.13
> tree into his kvm-ppc-queue tree, as there are some important bugfixes
> in the for-3.13 tree that touch c
On 08.01.2014, at 11:25, Paul Mackerras wrote:
> This adds saving of the transactional memory (TM) checkpointed state
> on guest entry and exit. We only do this if we see that the guest has
> an active transaction.
>
> It also adds emulation of the TM state changes when delivering IRQs
> into
On 01/24/2014 07:08 PM, Konrad Rzeszutek Wilk wrote:
> On Thu, Jan 16, 2014 at 03:13:44PM +0100, Julian Stecklina wrote:
>> The paravirtualized clock used in KVM and Xen uses a version field to
>> allow the guest to see when the shared data structure is inconsistent.
>> The code reads the version f
On 08.01.2014, at 11:25, Paul Mackerras wrote:
> From: Michael Neuling
>
> Add new state for transactional memory (TM) to kvm_vcpu_arch. Also add
> asm-offset bits that are going to be required.
>
> This also moves the existing TFHAR, TFIAR and TEXASR SPRs into a
> CONFIG_PPC_TRANSACTIONAL_M
On 24/01/14 23:37, Christoffer Dall wrote:
> On Sat, Jan 04, 2014 at 08:27:23AM -0800, Christoffer Dall wrote:
>> The stage-2 memory attributes are distinct from the Hyp memory
>> attributes and the Stage-1 memory attributes. We were using the stage-1
>> memory attributes for stage-2 mappings caus
On 08.01.2014, at 11:25, Paul Mackerras wrote:
> Currently in book3s_hv_rmhandlers.S we have three places where we
> have woken up from nap mode and we check the reason field in SRR1
> to see what event woke us up. This consolidates them into a new
> function, kvmppc_check_wake_reason. It look
https://bugzilla.kernel.org/show_bug.cgi?id=69361
Alan changed:
What|Removed |Added
Status|NEW |RESOLVED
CC|
On 27.01.2014, at 11:28, Aneesh Kumar K.V
wrote:
> Alexander Graf writes:
>
>> On 21.01.2014, at 10:42, Aneesh Kumar K.V
>> wrote:
>>
>>> Liu Ping Fan writes:
>>>
To make sure that on host, the pages marked with _PAGE_NUMA result in a
fault
when guest access them, we shou
On Mon, Jan 27, 2014 at 10:11:40AM +0100, Alexander Graf wrote:
>
> On 21.01.2014, at 10:42, Aneesh Kumar K.V
> wrote:
>
> > Liu Ping Fan writes:
> >
> >> To make sure that on host, the pages marked with _PAGE_NUMA result in a
> >> fault
> >> when guest access them, we should force the check
Alexander Graf writes:
> On 21.01.2014, at 10:42, Aneesh Kumar K.V
> wrote:
>
>> Liu Ping Fan writes:
>>
>>> To make sure that on host, the pages marked with _PAGE_NUMA result in a
>>> fault
>>> when guest access them, we should force the checking when guest uses
>>> hypercall
>>> to setup
On 27 January 2014 07:52, Alexander Graf wrote:
>
> On 26.01.2014, at 06:43, Victor Kamensky wrote:
>> Scott's definition interpretation does not depend on CPU type.
>> It is much simpler. It does not use notion not very well defined
>> like "real bus". it does not use word 'endianness', byteswap
https://bugzilla.kernel.org/show_bug.cgi?id=69491
--- Comment #3 from Kashyap Chamarthy ---
Created attachment 123541
--> https://bugzilla.kernel.org/attachment.cgi?id=123541&action=edit
Complete stdout of `x86info -a`
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https://bugzilla.kernel.org/show_bug.cgi?id=69491
Kashyap Chamarthy changed:
What|Removed |Added
Summary|Booting into Intel Haswell |Booting into a guest on
https://bugzilla.kernel.org/show_bug.cgi?id=69491
--- Comment #2 from Kashyap Chamarthy ---
Created attachment 123511
--> https://bugzilla.kernel.org/attachment.cgi?id=123511&action=edit
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--- Comment #1 from Kashyap Chamarthy ---
Created attachment 123501
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Complete stdout of dmesg
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Kashyap Chamarthy changed:
What|Removed |Added
Status|NEW |RESOLVED
Resolution|---
On 21.01.2014, at 10:42, Aneesh Kumar K.V
wrote:
> Liu Ping Fan writes:
>
>> To make sure that on host, the pages marked with _PAGE_NUMA result in a fault
>> when guest access them, we should force the checking when guest uses
>> hypercall
>> to setup hpte.
>>
>> Signed-off-by: Liu Ping Fan
https://bugzilla.kernel.org/show_bug.cgi?id=69491
Bug ID: 69491
Summary: Booting into Intel Haswell (baremetal) crashes with
soft lockup [qemu-system-x86:911]
Product: Virtualization
Version: unspecified
Kernel Version: 3.14.0-0.
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