If kvm_io_bus_register_dev() fails then it returns success but it should
return an error code.
I also did a little cleanup like removing an impossible NULL test.
Fixes: 2b3c246a682c ('KVM: Make coalesced mmio use a device per zone')
Signed-off-by: Dan Carpenter
diff --git a/virt/kvm/coalesced_m
On Tue, Jan 28, 2014 at 09:28:45AM -0600, Brian King wrote:
Thanks for the review, Brian!
> These look like they will conflict with a recent patch to
> the ipr driver:
>
> http://www.spinics.net/lists/linux-scsi/msg71644.html
BTW, this one does not appear ACKed.
> Do you want me to rediff your
On Fri, Jan 17, 2014 at 02:00:32PM -0700, Bjorn Helgaas wrote:
> > Bjorn,
> >
> > As the release is supposedly this weekend, do you prefer
> > the patches to go to your tree or to individual trees after
> > the release?
>
> I'd be happy to merge them, except for the fact that they probably
> would
Am 29.01.2014 14:16, schrieb Dan Carpenter:
> If kvm_io_bus_register_dev() fails then it returns success but it should
> return an error code.
>
> I also did a little cleanup like removing an impossible NULL test.
>
> Fixes: 2b3c246a682c ('KVM: Make coalesced mmio use a device per zone')
> Sign
2014-01-21 Daniel Raho :
> Hello,
>
> You might be interested to know that Virtual Open Systems has updated
> its KVM on Samsung's ARM Chromebook guide. The new guide is available
> at http://virtualopensystems.com/en/solutions/guides/kvm-on-chromebook/
>
> Accessing the full content of this guide
On Wed, Jan 29, 2014 at 02:57:21PM +0100, walter harms wrote:
>
>
> Am 29.01.2014 14:16, schrieb Dan Carpenter:
> > If kvm_io_bus_register_dev() fails then it returns success but it should
> > return an error code.
> >
> > I also did a little cleanup like removing an impossible NULL test.
> >
>
On 01/28/2014 05:28 PM, Christoffer Dall wrote:
The KVM API documentation is not clear about the semantics of the data
field on the mmio struct on the kvm_run struct.
This has become problematic when supporting ARM guests on big-endian
host systems with guests of both endianness types, because i
On Tue, Jan 28, 2014 at 07:16:11PM +0100, María Soler Heredia wrote:
> Hello Andrew,
>
> I have been experimenting a little with your tests and I have some comments
> and questions. I have already compiled and run versions v1 and v2, which
> work with kvm disabled, but I cannot run v3 using the sa
From: Gleb Natapov
XICS failed to free xics structure on error path. MPIC destroy handler
forgot to delete kvm_device structure.
Signed-off-by: Gleb Natapov
Acked-by: Paul Mackerras
Signed-off-by: Alexander Graf
---
arch/powerpc/kvm/book3s_xics.c | 4 +++-
arch/powerpc/kvm/mpic.c| 1
Hi Paolo & Gleb,
This is my current patch queue for ppc. Please pull.
Highlights in this release are:
- automatic module loading
- book3s hv: little endian guest support
- booke: use proper caching attributes for non-ram
- minor optimizations / bug fixes
- book3s hv: first part of POW
From: Liu Ping Fan
In some scene, e.g openstack CI, PR guest can trigger "sc 1" frequently,
this patch optimizes the path by directly delivering BOOK3S_INTERRUPT_SYSCALL
to HV guest, so powernv can return to HV guest without heavy exit, i.e,
no need to swap TLB, HTAB,.. etc
Signed-off-by: Liu Pi
From: Anton Blanchard
We create a guest MSR from scratch when delivering exceptions in
a few places. Instead of extracting LPCR[ILE] and inserting it
into MSR_LE each time, we simply create a new variable intr_msr which
contains the entire MSR to use. For a little-endian guest, userspace
needs
From: Michael Neuling
There are no processors in existence that have TM but no VMX or VSX. So let's
makes CONFIG_PPC_TRANSACTIONAL_MEM select both CONFIG_VSX and CONFIG_ALTIVEC.
This makes the code a lot simpler by removing the need for a bunch of #ifdefs.
Signed-off-by: Michael Neuling
Signed
From: Paul Mackerras
POWER8 has a bit in the LPCR to enable or disable the PURR and SPURR
registers to count when in the guest. Set this bit.
POWER8 has a field in the LPCR called AIL (Alternate Interrupt Location)
which is used to enable relocation-on interrupts. Allow userspace to
set this f
From: Michael Neuling
This adds the software abort code defines for transactional memory (TM).
These values are from PAPR.
Signed-off-by: Michael Neuling
Signed-off-by: Paul Mackerras
Signed-off-by: Alexander Graf
---
arch/powerpc/include/uapi/asm/tm.h | 2 ++
1 file changed, 2 insertions(+)
From: Paul Mackerras
When the PR host is running on a POWER8 machine in POWER8 mode, it
will use doorbell interrupts for IPIs. If one of them arrives while
we are in the guest, we pop out of the guest with trap number 0xA00,
which isn't handled by kvmppc_handle_exit_pr, leading to the following
From: Michael Neuling
Add new state for transactional memory (TM) to kvm_vcpu_arch. Also add
asm-offset bits that are going to be required.
This also moves the existing TFHAR, TFIAR and TEXASR SPRs into a
CONFIG_PPC_TRANSACTIONAL_MEM section. This requires some code changes to
ensure we still
From: Paul Mackerras
POWER8 has support for hypervisor doorbell interrupts. Though the
kernel doesn't use them for IPIs on the powernv platform yet, it
probably will in future, so this makes KVM cope gracefully if a
hypervisor doorbell interrupt arrives while in a guest.
Signed-off-by: Paul Mac
From: Paul Mackerras
The load_up_fpu and load_up_altivec functions were never intended to
be called from C, and do things like modifying the MSR value in their
callers' stack frames, which are assumed to be interrupt frames. In
addition, on 32-bit Book S they require the MMU to be off.
This mak
From: Paul Mackerras
* SRR1 wake reason field for system reset interrupt on wakeup from nap
is now a 4-bit field on P8, compared to 3 bits on P7.
* Set PECEDP in LPCR when napping because of H_CEDE so guest doorbells
will wake us up.
* Waking up from nap because of a guest doorbell interrup
From: Paul Mackerras
This allows us to select architecture 2.05 (POWER6) or 2.06 (POWER7)
compatibility modes on a POWER8 processor. (Note that transactional
memory is disabled for usermode if either or both of the PCR_TM_DIS
and PCR_ARCH_206 bits are set.)
Signed-off-by: Paul Mackerras
Signed
From: Michael Ellerman
At present this should never happen, since the host kernel sets
HFSCR to allow access to all facilities. It's better to be prepared
to handle it cleanly if it does ever happen, though.
Signed-off-by: Michael Ellerman
Signed-off-by: Paul Mackerras
Signed-off-by: Alexande
From: Paul Mackerras
Currently in book3s_hv_rmhandlers.S we have three places where we
have woken up from nap mode and we check the reason field in SRR1
to see what event woke us up. This consolidates them into a new
function, kvmppc_check_wake_reason. It looks at the wake reason
field in SRR1,
From: Paul Mackerras
On a threaded processor such as POWER7, we group VCPUs into virtual
cores and arrange that the VCPUs in a virtual core run on the same
physical core. Currently we don't enforce any correspondence between
virtual thread numbers within a virtual core and physical thread
number
From: Michael Neuling
POWER8 doesn't have the DABR and DABRX registers; instead it has
new DAWR/DAWRX registers, which will be handled in a later patch.
Signed-off-by: Michael Neuling
Signed-off-by: Paul Mackerras
Signed-off-by: Alexander Graf
---
arch/powerpc/kvm/book3s_hv_interrupts.S | 2
From: Mihai Caraman
Use gva_t instead of unsigned int for eaddr in deliver_tlb_miss().
Signed-off-by: Mihai Caraman
CC: sta...@vger.kernel.org
Signed-off-by: Alexander Graf
---
arch/powerpc/kvm/e500_mmu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/powerpc/kvm/e50
From: Paul Mackerras
POWER8 has 512 sets in the TLB, compared to 128 for POWER7, so we need
to do more tlbiel instructions when flushing the TLB on POWER8.
Signed-off-by: Paul Mackerras
Signed-off-by: Alexander Graf
---
arch/powerpc/kvm/book3s_hv_rmhandlers.S | 8 +++-
1 file changed, 7 i
From: Cédric Le Goater
MMIO emulation reads the last instruction executed by the guest
and then emulates. If the guest is running in Little Endian order,
or more generally in a different endian order of the host, the
instruction needs to be byte-swapped before being emulated.
This patch adds a h
From: Bharat Bhushan
kvm_hypercall() have nothing KVM specific, so renamed to epapr_hypercall().
Also this in moved to arch/powerpc/include/asm/epapr_hcalls.h
Signed-off-by: Bharat Bhushan
Signed-off-by: Alexander Graf
---
arch/powerpc/include/asm/epapr_hcalls.h | 46 +
We had code duplication between the inline functions to get our last
instruction on normal interrupts and system call interrupts. Unify
both helper functions towards a single implementation.
Signed-off-by: Alexander Graf
---
arch/powerpc/include/asm/kvm_book3s.h | 18 +++---
1 file c
From: Michael Neuling
This adds fields to the struct kvm_vcpu_arch to store the new
guest-accessible SPRs on POWER8, adds code to the get/set_one_reg
functions to allow userspace to access this state, and adds code to
the guest entry and exit to context-switch these SPRs between host
and guest.
From: Bharat Bhushan
lookup_linux_pte() is doing more than lookup, updating the pte,
so for clarity it is renamed to lookup_linux_pte_and_update()
Signed-off-by: Bharat Bhushan
Reviewed-by: Scott Wood
Signed-off-by: Alexander Graf
---
arch/powerpc/kvm/book3s_hv_rm_mmu.c | 8 +---
1 file
From: Andreas Schwab
Signed-off-by: Andreas Schwab
CC: sta...@vger.kernel.org
Signed-off-by: Alexander Graf
---
arch/powerpc/kvm/book3s_hv.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/arch/powerpc/kvm/book3s_hv.c b/arch/powerpc/kvm/book3s_hv.c
index 461f555..7e18
From: Bharat Bhushan
kvm_hypercall0() and friends have nothing KVM specific so moved to
epapr_hypercall0() and friends. Also they are moved from
arch/powerpc/include/asm/kvm_para.h to arch/powerpc/include/asm/epapr_hcalls.h
Signed-off-by: Bharat Bhushan
Signed-off-by: Alexander Graf
---
arch/
From: Tiejun Chen
Rather than calling hard_irq_disable() when we're back in C code
we can just call RECONCILE_IRQ_STATE to soft disable IRQs while
we're already in hard disabled state.
This should be functionally equivalent to the code before, but
cleaner and faster.
Signed-off-by: Tiejun Chen
From: Zhouyi Zhou
NULL return of kvmppc_mmu_hpte_cache_next should be handled
Signed-off-by: Zhouyi Zhou
Signed-off-by: Alexander Graf
---
arch/powerpc/kvm/book3s_32_mmu_host.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/powerpc/kvm/book3s_32_mmu_host.c
b/arch/powerpc/kvm/b
From: Bharat Bhushan
KVM uses same WIM tlb attributes as the corresponding qemu pte.
For this we now search the linux pte for the requested page and
get these cache caching/coherency attributes from pte.
Signed-off-by: Bharat Bhushan
Reviewed-by: Scott Wood
Signed-off-by: Alexander Graf
---
Systems that support automatic loading of kernel modules through
device aliases should try and automatically load kvm when /dev/kvm
gets opened.
Add code to support that magic for all PPC kvm targets, even the
ones that don't support modules yet.
Signed-off-by: Alexander Graf
---
arch/powerpc/k
From: Paul Mackerras
This modifies kvmppc_load_fp and kvmppc_save_fp to use the generic
FP/VSX and VMX load/store functions instead of open-coding the
FP/VSX/VMX load/store instructions. Since kvmppc_load/save_fp don't
follow C calling conventions, we make them private symbols within
book3s_hv_r
From: Bharat Bhushan
On booke, "struct tlbe_ref" contains host tlb mapping information
(pfn: for guest-pfn to pfn, flags: attribute associated with this mapping)
for a guest tlb entry. So when a guest creates a TLB entry then
"struct tlbe_ref" is set to point to valid "pfn" and set attributes in
From: Paul Mackerras
This uses struct thread_fp_state and struct thread_vr_state to store
the floating-point, VMX/Altivec and VSX state, rather than flat arrays.
This makes transferring the state to/from the thread_struct simpler
and allows us to unify the get/set_one_reg implementations for the
From: Bharat Bhushan
We need to search linux "pte" to get "pte" attributes for setting TLB in KVM.
This patch defines a lookup_linux_ptep() function which returns pte pointer.
Signed-off-by: Bharat Bhushan
Reviewed-by: Scott Wood
Signed-off-by: Alexander Graf
---
arch/powerpc/include/asm/pgt
From: Scott Wood
Simplify the handling of lazy EE by going directly from fully-enabled
to hard-disabled. This replaces the lazy_irq_pending() check
(including its misplaced kvm_guest_exit() call).
As suggested by Tiejun Chen, move the interrupt disabling into
kvmppc_prepare_to_enter() rather th
From: Paul Mackerras
Now that we have the vcpu floating-point and vector state stored in
the same type of struct as the main kernel uses, we can load that
state directly from the vcpu struct instead of having extra copies
to/from the thread_struct. Similarly, when the guest state needs to
be sav
On 01/28/2014 05:44 PM, Aneesh Kumar K.V wrote:
We definitely don't need to emulate mtspr, because both the registers
are hypervisor resource.
This patch description doesn't cover what the patch actually does. It
changes the implementation from "always tell the guest it uses 100%" to
"give th
On 01/28/2014 05:44 PM, Aneesh Kumar K.V wrote:
Writing to IC is not allowed in the privileged mode.
This is not a patch description.
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/kvm_host.h | 1 +
arch/powerpc/kvm/book3s_emulate.c | 3 +++
arch/powerpc/kvm/book3s_pr.c
On 01/28/2014 05:44 PM, Aneesh Kumar K.V wrote:
virtual time base register is a per vm register and need to saved
and restored on vm exit and entry. Writing to VTB is not allowed
in the privileged mode.
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/kvm_host.h | 1 +
arch/powe
Self explanatory.
Reported-by: Radim Krcmar
Cc: Vadim Rozenfeld
Signed-off-by: Paolo Bonzini
---
arch/x86/kvm/x86.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c
index 34d0d610aa8a..39c28f09dfd5 100644
--- a/arch/x86/kvm/x86.c
+++ b
On 01/28/2014 05:44 PM, Aneesh Kumar K.V wrote:
We allow priv-mode update of this. The guest value is saved in fscr,
and the value actually used is saved in shadow_fscr. shadow_fscr
only contains values that are allowed by the host. On
facility unavailable interrupt, if the facility is allowed by
Il 29/01/2014 17:12, Alexander Graf ha scritto:
git://github.com/agraf/linux-2.6.git kvm-ppc-next
Pulled. There were a couple of conflicts, but I didn't have to scratch
my head too long. :)
Thanks,
Paolo
--
To unsubscribe from this list: send the line "unsubscribe kvm" in
the body of a m
On 01/28/2014 05:44 PM, Aneesh Kumar K.V wrote:
Runtime disable transactional memory feature looking at pa-features
device tree entry. We need to do this so that we can run a kernel
built with TM config in PR mode. For PR guest we provide a device
tree entry with TM feature disabled in pa-feature
On 01/28/2014 05:44 PM, Aneesh Kumar K.V wrote:
At this point we allow all the supported facilities except EBB. So
forward the interrupt to guest as illegal instruction.
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/include/asm/kvm_asm.h | 4 +++-
arch/powerpc/kvm/book3s.c | 4
Linus,
The following changes since commit 0dc3fd0249a295863900984e02dd4bb89204205b:
Merge tag 'modules-next-for-linus' of
git://git.kernel.org/pub/scm/linux/kernel/git/rusty/linux (2014-01-22 22:30:15
-0800)
are available in the git repository at:
git://git.kernel.org/pub/scm/virt/kvm/kvm
Remove unused last_kernel_ns variable.
Signed-off-by: Marcelo Tosatti
diff --git a/arch/x86/include/asm/kvm_host.h b/arch/x86/include/asm/kvm_host.h
index fdf83af..0ffe714 100644
--- a/arch/x86/include/asm/kvm_host.h
+++ b/arch/x86/include/asm/kvm_host.h
@@ -444,7 +444,6 @@ struct kvm_vcpu_arch
On Wed, Jan 22, 2014 at 02:56:33PM +, Marc Zyngier wrote:
> In order for the guest with caches off to observe data written
> contained in a given page, we need to make sure that page is
> committed to memory, and not just hanging in the cache (as
> guest accesses are completely bypassing the ca
On Wed, Jan 22, 2014 at 02:56:34PM +, Marc Zyngier wrote:
> The current handling of AArch32 trapping is slightly less than
> perfect, as it is not possible (from a handler point of view)
> to distinguish it from an AArch64 access, nor to tell a 32bit
> from a 64bit access either.
>
> Fix this
On Wed, Jan 22, 2014 at 02:56:36PM +, Marc Zyngier wrote:
> When the guest runs with caches disabled (like in an early boot
> sequence, for example), all the writes are diectly going to RAM,
> bypassing the caches altogether.
>
> Once the MMU and caches are enabled, whatever sits in the cache
On Wed, Jan 22, 2014 at 02:56:42PM +, Marc Zyngier wrote:
> HCR.TVM traps (among other things) accesses to AMAIR0 and AMAIR1.
> In order to minimise the amount of surprise a guest could generate by
> trying to access these registers with caches off, add them to the
> list of registers we switch
On Wed, Jan 22, 2014 at 02:56:38PM +, Marc Zyngier wrote:
> Commit 240e99cbd00a (ARM: KVM: Fix 64-bit coprocessor handling)
> changed the way we match the 64bit coprocessor access from
> user space, but didn't update the trap handler for the same
> set of registers.
>
> The effect is that a tr
On Wed, Jan 22, 2014 at 02:56:41PM +, Marc Zyngier wrote:
> In order to be able to detect the point where the guest enables
> its MMU and caches, trap all the VM related system registers.
>
> Once we see the guest enabling both the MMU and the caches, we
> can go back to a saner mode of operat
On Wed, Jan 22, 2014 at 02:56:39PM +, Marc Zyngier wrote:
> Commit 240e99cbd00a (ARM: KVM: Fix 64-bit coprocessor handling)
> added an ordering dependency for the 64bit registers.
>
> The order described is: CRn, CRm, Op1, Op2, 64bit-first.
>
> Unfortunately, the implementation is: CRn, 64bit
On Wed, Jan 22, 2014 at 02:56:37PM +, Marc Zyngier wrote:
> In order for the guest with caches off to observe data written
nit: s/the guest/a guest/
nit: s/caches off/caches disabled/
> contained in a given page, we need to make sure that page is
> committed to memory, and not just hanging in
On Wed, Jan 22, 2014 at 02:56:35PM +, Marc Zyngier wrote:
> In order to be able to detect the point where the guest enables
> its MMU and caches, trap all the VM related system registers.
>
> Once we see the guest enabling both the MMU and the caches, we
> can go back to a saner mode of operat
On Wed, Jan 22, 2014 at 02:56:40PM +, Marc Zyngier wrote:
> So far, KVM/ARM used a fixed HCR configuration per guest, except for
> the VI/VF/VA bits to control the interrupt in absence of VGIC.
>
> With the upcoming need to dynamically reconfigure trapping, it becomes
> necessary to allow the
On Fri, Jan 17, 2014 at 05:02:21PM +0100, Alexander Gordeev wrote:
> As result deprecation of MSI-X/MSI enablement functions
> pci_enable_msix() and pci_enable_msi_block() all drivers
> using these two interfaces need to be updated to use the
> new pci_enable_msi_range() and pci_enable_msix_range()
On Sat, Jan 18, 2014 at 09:59:40AM -0500, Tejun Heo wrote:
> On Sat, Jan 18, 2014 at 07:38:55AM -0700, Bjorn Helgaas wrote:
> > On Sat, Jan 18, 2014 at 12:15 AM, Alexander Gordeev
> > wrote:
> > > On Fri, Jan 17, 2014 at 02:00:32PM -0700, Bjorn Helgaas wrote:
> > >> > As the release is supposedly
On Wed, 2014-01-29 at 17:39 +0100, Alexander Graf wrote:
> static inline mfvtb(unsigned long)
> {
> #ifdef CONFIG_PPC_BOOK3S_64
> return mfspr(SPRN_VTB);
> #else
> BUG();
> #endif
> }
>
> is a lot easier to read and get right. But reg.h is Ben's call.
Agreed.
> Also could you please gi
On Thu, 2014-01-30 at 09:54 +1100, Benjamin Herrenschmidt wrote:
> On Wed, 2014-01-29 at 17:39 +0100, Alexander Graf wrote:
> > static inline mfvtb(unsigned long)
> > {
> > #ifdef CONFIG_PPC_BOOK3S_64
> > return mfspr(SPRN_VTB);
> > #else
> > BUG();
> > #endif
> > }
> >
> > is a lot easi
Hi
I would like to measure the performance of KVM by using hardware
performance counters and I have some questions
1. if i want to get the amount of time spent in instruction and device
emulation, should i use oprofile on the kvm process on the host
machine ?
2. what about amount of time spent in
On Tue, Jan 28, 2014 at 10:14:12PM +0530, Aneesh Kumar K.V wrote:
> We allow priv-mode update of this. The guest value is saved in fscr,
> and the value actually used is saved in shadow_fscr. shadow_fscr
> only contains values that are allowed by the host. On
> facility unavailable interrupt, if th
On Tue, Jan 28, 2014 at 10:14:07PM +0530, Aneesh Kumar K.V wrote:
> virtual time base register is a per vm register and need to saved
> and restored on vm exit and entry. Writing to VTB is not allowed
> in the privileged mode.
...
> +#ifdef CONFIG_PPC_BOOK3S_64
> +#define mfvtb() ({un
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