On Tue, Apr 29, 2014 at 06:17:37PM +0200, Alexander Graf wrote:
> When we expose a POWER8 CPU into the guest, it will start accessing PMU SPRs
> that we don't emulate. Just ignore accesses to them.
>
> Signed-off-by: Alexander Graf
This patch is OK as it stands, but in fact the architecture says
Read guest last instruction from kvmppc_get_last_inst() allowing the function
to fail in order to emulate again. On bookehv architecture search for
the physical address and kmap it, instead of using Load External PID (lwepx)
instruction. This fixes an infinite loop caused by lwepx's data TLB miss
e
Read guest last instruction from kvmppc_get_last_inst() allowing the function
to fail in order to emulate again. On bookehv architecture search for
the physical address and kmap it, instead of using Load External PID (lwepx)
instruction. This fixes an infinite loop caused by lwepx's data TLB miss
e
On bookehv vcpu's last instruction is read using load external pid
(lwepx) instruction. lwepx exceptions (DTLB_MISS, DSI and LRAT) need
to be handled by KVM. These exceptions originate from host state
(MSR[GS] = 0) which implies additional checks in DO_KVM macro (beside
the current MSR[GS] = 1) by
The commit 1d628af7 "add load inst fixup" made an attempt to handle
failures generated by reading the guest current instruction. The fixup
code that was added works by chance hiding the real issue.
Load external pid (lwepx) instruction, used by KVM to read guest
instructions, is executed in a subs
Add defines MAS0_GET_TLBSEL() and MAS1_GET_TSIZE() to Book3E.
Signed-off-by: Mihai Caraman
---
v2:
- no change
arch/powerpc/include/asm/mmu-book3e.h | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/arch/powerpc/include/asm/mmu-book3e.h
b/arch/powerpc/include/asm/mmu-b
On book3e, guest last instruction was read on the exist path using load
external pid (lwepx) dedicated instruction. lwepx failures have to be
handled by KVM and this would require additional checks in DO_KVM hooks
(beside MSR[GS] = 1). However extra checks on host fast path are commonly
considered
On 04/30/2014 06:59 PM, Luis R. Rodriguez wrote:
> On Wed, Apr 30, 2014 at 04:04:34PM -0400, Vlad Yasevich wrote:
>> On 04/22/2014 03:43 PM, Luis R. Rodriguez wrote:
>>> diff --git a/net/bridge/br_if.c b/net/bridge/br_if.c
>>> index 54d207d..dcd9378 100644
>>> --- a/net/bridge/br_if.c
>>> +++ b/net
On Wed, Apr 30, 2014 at 04:04:34PM -0400, Vlad Yasevich wrote:
> On 04/22/2014 03:43 PM, Luis R. Rodriguez wrote:
> > diff --git a/net/bridge/br_if.c b/net/bridge/br_if.c
> > index 54d207d..dcd9378 100644
> > --- a/net/bridge/br_if.c
> > +++ b/net/bridge/br_if.c
> > @@ -315,6 +315,8 @@ netdev_featu
On 04/22/2014 03:43 PM, Luis R. Rodriguez wrote:
> On Tue, Mar 18, 2014 at 02:22:43PM -0700, Luis R. Rodriguez wrote:
>> On Tue, Mar 18, 2014 at 01:46:49PM -0700, Cong Wang wrote:
>>> On Fri, Mar 14, 2014 at 6:39 PM, Luis R. Rodriguez wrote:
On Thu, Mar 13, 2014 at 11:26:25AM -0700, Cong Wang
Il 30/04/2014 13:15, Christoffer Dall ha scritto:
The following changes since commit 0f689a33ad17845363acdc6d52783befd6ad116c:
Merge branch 'for-linus' of
git://git.kernel.org/pub/scm/linux/kernel/git/s390/linux (2014-04-16 11:28:25
-0700)
are available in the git repository at:
git://g
On 04/22/2014 03:41 PM, Luis R. Rodriguez wrote:
> On Wed, Mar 19, 2014 at 7:05 PM, Luis R. Rodriguez wrote:
>> On Tue, Mar 18, 2014 at 08:10:56PM -0700, Stephen Hemminger wrote:
>>> On Wed, 12 Mar 2014 20:15:25 -0700
>>> "Luis R. Rodriguez" wrote:
>>>
As it is now if you add create a bridge
On Tue, Apr 22, 2014 at 12:41 PM, Luis R. Rodriguez
wrote:
> Stephen, I'd like to respin this series to address all pending
> feedback, I'd still like your feedback / call / judgement on this
> part. I'm fine either way, just wanted to ensure I highlight the
> reasoning of why I kept the original
On Tue, Apr 22, 2014 at 12:43 PM, Luis R. Rodriguez wrote:
> On Tue, Mar 18, 2014 at 02:22:43PM -0700, Luis R. Rodriguez wrote:
>> On Tue, Mar 18, 2014 at 01:46:49PM -0700, Cong Wang wrote:
>> > On Fri, Mar 14, 2014 at 6:39 PM, Luis R. Rodriguez wrote:
>> > > On Thu, Mar 13, 2014 at 11:26:25AM -0
The L1 instruction cache control register contains bits that indicate
that we're still handling a request. Mask those out when we set the SPR
so that a read doesn't assume we're still doing something.
Signed-off-by: Alexander Graf
---
arch/powerpc/kvm/e500_emulate.c | 1 +
1 file changed, 1 inse
The dcbtls instruction is able to lock data inside the L1 cache.
We don't want to give the guest actual access to hardware cache locks,
as that could influence other VMs on the same system. But we can tell
the guest that its locking attempt failed.
By implementing the instruction we at least don'
(CCing Juan)
On Tue, Apr 29, 2014 at 09:39:03PM -0300, Marcelo Tosatti wrote:
> Check vmsd for unmigratable field, allowing migratibility status
> to be modified after vmstate_register.
>
> Signed-off-by: Marcelo Tosatti
Reviewed-by: Eduardo Habkost
>
> diff --git a/savevm.c b/savevm.c
> ind
On Mon, Apr 28, 2014 at 09:08:10PM +0100, Alex Williamson wrote:
> On Mon, 2014-04-28 at 20:19 +0100, Will Deacon wrote:
> > Please excuse any ignorance on part here (I'm not at all familiar with the
> > Intel IOMMU), but shouldn't this really be a property of the interrupt
> > controller itself? O
On Wed, Apr 30, 2014 at 10:56:41AM +0100, Marc Zyngier wrote:
> On 29/04/14 20:44, Christoffer Dall wrote:
> > On Tue, Apr 29, 2014 at 11:24:13AM +0530, Anup Patel wrote:
> >> Currently, KVM ARM/ARM64 only provides in-kernel emulation of Power State
> >> and Coordination Interface (PSCI) v0.1.
> >>
From: Andre Przywara
Since KVM internally represents the ICFGR registers by stuffing two
of them into one word, the offset for accessing the internal
representation and the one for the MMIO based access are different.
So keep the original offset around, but adjust the internal array
offset by one
From: Will Deacon
KVM currently crashes and burns on big-endian hosts, so don't allow it
to be selected until we've got that fixed.
Cc: Marc Zyngier
Signed-off-by: Will Deacon
Signed-off-by: Christoffer Dall
---
arch/arm/kvm/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff
From: Mark Salter
The kvm/mmu code shared by arm and arm64 uses kalloc() to allocate
a bounce page (if hypervisor init code crosses page boundary) and
hypervisor PGDs. The problem is that kalloc() does not guarantee
the proper alignment. In the case of the bounce page, the page sized
buffer alloc
From: Haibin Wang
When dispatch SGI(mode == 0), that is the vcpu of VM should send
sgi to the cpu which the target_cpus list.
So, there must add the "break" to branch of case 0.
Cc: # 3.10+
Signed-off-by: Haibin Wang
Acked-by: Marc Zyngier
Signed-off-by: Christoffer Dall
---
virt/kvm/arm/vg
From: Haibin Wang
Currently below check in vgic_ioaddr_overlap will always succeed,
because the vgic dist base and vgic cpu base are still kept UNDEF
after initialization. The code as follows will be return forever.
if (IS_VGIC_ADDR_UNDEF(dist) || IS_VGIC_ADDR_UNDEF(cpu))
The following changes since commit 0f689a33ad17845363acdc6d52783befd6ad116c:
Merge branch 'for-linus' of
git://git.kernel.org/pub/scm/linux/kernel/git/s390/linux (2014-04-16 11:28:25
-0700)
are available in the git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/kvmarm/kvmarm
Il 29/04/2014 15:36, Christian Borntraeger ha scritto:
git://git.kernel.org/pub/scm/linux/kernel/git/kvms390/linux.git
tags/kvm-s390-20140429
Pulled. I still plan to go through the 50+ patch pull request and do at
least some kind of API review.
kvm/queue will be updated today hopefully.
On 30/04/14 10:07, Heiko Carstens wrote:
> On Tue, Apr 29, 2014 at 03:36:43PM +0200, Christian Borntraeger wrote:
>> +static int handle_mvpg_pei(struct kvm_vcpu *vcpu)
>> +{
>> +unsigned long hostaddr, srcaddr, dstaddr;
>> +psw_t *psw = &vcpu->arch.sie_block->gpsw;
>> +struct mm_struct
On 30.04.14 07:51, Michael Neuling wrote:
In parallel to the Processor ID Register (PIR) threaded POWER8 also adds a
Thread ID Register (TID). Since PR KVM doesn't emulate more than one thread
s/TID/TIR/ above
Oops :)
per core, we can just always expose 0 here.
I'm not sure if we ever do
On 29/04/14 20:44, Christoffer Dall wrote:
> On Tue, Apr 29, 2014 at 11:24:13AM +0530, Anup Patel wrote:
>> Currently, KVM ARM/ARM64 only provides in-kernel emulation of Power State
>> and Coordination Interface (PSCI) v0.1.
>>
>> This patchset aims at providing newer PSCI v0.2 for KVM ARM/ARM64 VC
On 30.04.14 07:09, Michael Neuling wrote:
This patch series implements split core mode on POWER8. This enables up to 4
subcores per core which can each independently run guests (per guest SPRs like
SDR1, LPIDR etc are replicated per subcore). Lots more documentation on this
feature in the code
On Wed, 30 Apr 2014 10:07:09 +0200
Heiko Carstens wrote:
> On Tue, Apr 29, 2014 at 03:36:43PM +0200, Christian Borntraeger wrote:
> > +static int handle_mvpg_pei(struct kvm_vcpu *vcpu)
> > +{
> > + unsigned long hostaddr, srcaddr, dstaddr;
> > + psw_t *psw = &vcpu->arch.sie_block->gpsw;
> > +
On Tue, 29 Apr 2014 07:42:06 -0700, Christoffer Dall
wrote:
> On Fri, Mar 28, 2014 at 11:45:17AM -0700, Christoffer Dall wrote:
> > ARM VM System Specification
> > ===
> >
>
> I didn't receive a lot of comments on this one, I take this to mean that
> most people are happ
On Tue, Apr 29, 2014 at 03:36:43PM +0200, Christian Borntraeger wrote:
> +static int handle_mvpg_pei(struct kvm_vcpu *vcpu)
> +{
> + unsigned long hostaddr, srcaddr, dstaddr;
> + psw_t *psw = &vcpu->arch.sie_block->gpsw;
> + struct mm_struct *mm = current->mm;
> + int reg1, reg2, rc
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