1. How can I ensure that memory for the a guest is available and reserved?
In other words, I bring up a Linux VM which has 4G allocated, I want to make
sure it has all the 4G available right away.
I saw references to balloon driver, it seemed like that was more for dynamic
memory exchange
This adds support for the H_SET_MODE hcall. This hcall is a
multiplexer that has several functions, some of which are called
rarely, and some which are potentially called very frequently.
Here we add support for the functions that set the debug registers
CIABR (Completed Instruction Address
Am 29.05.2014 um 07:27 schrieb Paul Mackerras pau...@samba.org:
On Wed, May 28, 2014 at 03:27:32PM +0200, Alexander Graf wrote:
On 26.05.14 14:17, Paul Mackerras wrote:
+6.8 KVM_CAP_PPC_ENABLE_HCALL
+
+Architectures: ppc
+Parameters: args[0] is the PAPR hcall number
+args[1]
On Wed, May 28, 2014 at 05:46:39PM +0530, Raghavendra K T wrote:
In virtualized environment there are mainly three problems
related to spinlocks that affect performance.
1. LHP (lock holder preemption)
2. Lock Waiter Preemption (LWP)
3. Starvation/fairness
Though ticketlocks solve the
Hello,
Some more basic questions..
1. How can I ensure that memory for the a guest is available and
reserved? In other words, I bring up a Linux VM which has 4G
allocated, I want to make sure it has all the 4G available right away.
I saw references to balloon driver, it seemed like that
Am 29.05.2014 um 08:22 schrieb Michael Neuling mi...@neuling.org:
This adds support for the H_SET_MODE hcall. This hcall is a
multiplexer that has several functions, some of which are called
rarely, and some which are potentially called very frequently.
Here we add support for the
+/* Values for 2nd argument to H_SET_MODE */
+#define H_SET_MODE_RESOURCE_SET_CIABR1
+#define H_SET_MODE_RESOURCE_SET_DAWR2
+#define H_SET_MODE_RESOURCE_ADDR_TRANS_MODE3
+#define H_SET_MODE_RESOURCE_LE4
Much better, but I think you want to make use of
On Thu, May 29, 2014 at 01:40:08PM +0800, Gu Zheng wrote:
There was a patch(from Chen Fan, last august) about releasing vcpu when
closing vcpu fd http://www.spinics.net/lists/kvm/msg95701.html, but
your comment said Attempt where made to make it possible to destroy
individual vcpus
On Wed, May 28, 2014 at 11:42:00AM -0700, Mario Smarduch wrote:
emslot dirty_bitmap during and after write protect.
-Christoffer
Regarding huge pud that's causing some design problems, should huge PUD
pages be considered at all?
I'm not sure if there is any support for this on
On Wed, May 28, 2014 at 10:55:54AM -0700, Mario Smarduch wrote:
On 05/28/2014 01:09 AM, Christoffer Dall wrote:
On Tue, May 27, 2014 at 06:30:23PM -0700, Mario Smarduch wrote:
On 05/27/2014 01:19 PM, Christoffer Dall wrote:
On Thu, May 15, 2014 at 11:27:31AM -0700, Mario Smarduch wrote:
On Wed, May 28, 2014 at 05:00:48PM +0100, Marc Zyngier wrote:
On 25/05/14 16:35, Christoffer Dall wrote:
On Tue, May 20, 2014 at 05:55:43PM +0100, Marc Zyngier wrote:
[...]
+
+ /* DBGDSAR (32bit) */
+ { Op1( 0), CRn( 2), CRm( 0), Op2( 0), trap_raz_wi },
+
we don't handle access
On Wed, May 28, 2014 at 05:10:02PM +0100, Marc Zyngier wrote:
On 25/05/14 16:36, Christoffer Dall wrote:
On Tue, May 20, 2014 at 05:55:45PM +0100, Marc Zyngier wrote:
Enable trapping of the debug registers, preventing the guests to
mess with the host state (and allowing guests to use the
Here are a range of MIPS KVM TE fixes, preferably for v3.16 but I know
it's probably a bit late now. Changes are pretty minimal though since
v1 so please consider. They can also be found on my kvm_mips_queue
branch (and the kvm_mips_timer_v2 tag) here:
When MIPS KVM needs to write a TLB entry for the guest it reads the
CP0_Random register, uses it to generate the CP_Index, and writes the
TLB entry using the TLBWI instruction (tlb_write_indexed()).
However there's an instruction for that, TLBWR (tlb_write_random()) so
use that instead.
This
Each MIPS KVM guest has its own copy of the KVM exception vector. This
contains the TLB refill exception handler at offset 0x000, the general
exception handler at offset 0x180, and interrupt exception handlers at
offset 0x200 in case Cause_IV=1. A common handler is copied to offset
0x2000 and
When about to run the guest, deliver guest interrupts after disabling
host interrupts. This should prevent an hrtimer interrupt from being
handled after delivering guest interrupts, and therefore not delivering
the guest timer interrupt until after the next guest exit.
Signed-off-by: James Hogan
Fix build errors when DEBUG is defined in arch/mips/kvm/.
- The DEBUG code in kvm_mips_handle_tlbmod() was missing some variables.
- The DEBUG code in kvm_mips_host_tlb_write() was conditional on an
undefined debug variable.
- The DEBUG code in kvm_mips_host_tlb_inv() accessed asid_map
kvm_debug() uses pr_debug() which is already compiled out in the absence
of a DEBUG define, so remove the unnecessary ifdef DEBUG lines around
kvm_debug() calls which are littered around arch/mips/kvm/.
As well as generally cleaning up, this prevents future bit-rot due to
DEBUG not being commonly
Implement KVM_{GET,SET}_ONE_REG ioctl based access to the guest CP0
Count and Compare registers. These registers are special in that writing
to them has side effects (adjusting the time until the next timer
interrupt) and reading of Count depends on the time. Therefore add a
couple of callbacks so
The kvm_mips_comparecount_func() and kvm_mips_comparecount_wakeup()
functions are only used within arch/mips/kvm/kvm_mips.c, so make them
static.
Signed-off-by: James Hogan james.ho...@imgtec.com
Cc: Paolo Bonzini pbonz...@redhat.com
Cc: Gleb Natapov g...@kernel.org
Cc: kvm@vger.kernel.org
Cc:
Fix whitespace in struct kvm_mips_callbacks function pointers.
Signed-off-by: James Hogan james.ho...@imgtec.com
Cc: Paolo Bonzini pbonz...@redhat.com
Cc: Gleb Natapov g...@kernel.org
Cc: kvm@vger.kernel.org
Cc: Ralf Baechle r...@linux-mips.org
Cc: linux-m...@linux-mips.org
Cc: Sanjay Lal
Export the local_flush_icache_range function pointer for GPL modules so
that it can be used by KVM for syncing the icache after binary
translation of trapping instructions.
Signed-off-by: James Hogan james.ho...@imgtec.com
Cc: Paolo Bonzini pbonz...@redhat.com
Cc: Gleb Natapov g...@kernel.org
Cc:
MIPS KVM uses mips32_SyncICache to synchronise the icache with the
dcache after dynamically modifying guest instructions or writing guest
exception vector. However this uses rdhwr to get the SYNCI step, which
causes a reserved instruction exception on Ingenic XBurst cores.
It would seem to make
Implement KVM_{GET,SET}_ONE_REG ioctl based access to the guest CP0
HWREna register. This is so that userland can save and restore its
value so that RDHWR instructions don't have to be emulated by the guest.
Signed-off-by: James Hogan james.ho...@imgtec.com
Cc: Paolo Bonzini pbonz...@redhat.com
Expose the KVM guest CP0_Count frequency to userland via a new
KVM_REG_MIPS_COUNT_HZ register accessible with the KVM_{GET,SET}_ONE_REG
ioctls.
When the frequency is altered the bias is adjusted such that the guest
CP0_Count doesn't jump discontinuously or lose any timer interrupts.
Remove extra semicolon in kvm_arch_vcpu_dump_regs().
Signed-off-by: James Hogan james.ho...@imgtec.com
Cc: Paolo Bonzini pbonz...@redhat.com
Cc: Gleb Natapov g...@kernel.org
Cc: kvm@vger.kernel.org
Cc: Ralf Baechle r...@linux-mips.org
Cc: linux-m...@linux-mips.org
Cc: Sanjay Lal
The hrtimer callback for guest timer timeouts sets the guest's
CP0_Cause.TI bit to indicate to the guest that a timer interrupt is
pending, however there is no mutual exclusion implemented to prevent
this occurring while the guest's CP0_Cause register is being
read-modify-written elsewhere.
When
Contrary to the comment, the guest CP0_EPC register cannot be set via
kvm_regs, since it is distinct from the guest PC. Add the EPC register
to the KVM_{GET,SET}_ONE_REG ioctl interface.
Signed-off-by: James Hogan james.ho...@imgtec.com
Cc: Paolo Bonzini pbonz...@redhat.com
Cc: Gleb Natapov
The KVM_HOST_FREQ Kconfig symbol was used by KVM guest kernels to
override the timer frequency calculation to a value based on the host
frequency. Now that the KVM timer emulation is implemented independent
of the host timer frequency and defaults to 100MHz, adjust the working
of
Move the KVM_{GET,SET}_ONE_REG MIPS register id definitions out of
kvm_mips.c to kvm_host.h so that they can be shared between multiple
source files. This allows register access to be indirected depending on
the underlying implementation (trap emulate or VZ).
Signed-off-by: James Hogan
The logging from MIPS KVM is fairly noisy with kvm_info() in places
where it shouldn't be, such as on VM creation and migration to a
different CPU. Replace these kvm_info() calls with kvm_debug().
Signed-off-by: James Hogan james.ho...@imgtec.com
Cc: Paolo Bonzini pbonz...@redhat.com
Cc: Gleb
Implement KVM_{GET,SET}_ONE_REG ioctl based access to the guest CP0
UserLocal register. This is so that userland can save and restore its
value.
Signed-off-by: James Hogan james.ho...@imgtec.com
Cc: Paolo Bonzini pbonz...@redhat.com
Cc: Gleb Natapov g...@kernel.org
Cc: kvm@vger.kernel.org
Cc:
The kfree() function already NULL checks the parameter so remove the
redundant NULL checks before kfree() calls in arch/mips/kvm/.
Signed-off-by: James Hogan james.ho...@imgtec.com
Cc: Paolo Bonzini pbonz...@redhat.com
Cc: Gleb Natapov g...@kernel.org
Cc: kvm@vger.kernel.org
Cc: Ralf Baechle
Previously the emulation of the CPU timer was just enough to get a Linux
guest running but some shortcuts were taken:
- The guest timer interrupt was hard coded to always happen every 10 ms
rather than being timed to when CP0_Count would match CP0_Compare.
- The guest's CP0_Count register was
When a VCPU is scheduled in on a different CPU, refresh the hrtimer used
for emulating count/compare so that it gets migrated to the same CPU.
This should prevent a timer interrupt occurring on a different CPU to
where the guest it relates to is running, which would cause the guest
timer
Expose two new virtual registers to userland via the
KVM_{GET,SET}_ONE_REG ioctls.
KVM_REG_MIPS_COUNT_CTL is for timer configuration fields and just
contains a master disable count bit. This can be used by userland to
freeze the timer in order to read a consistent state from the timer
count value
On 05/29/2014 03:25 AM, Rik van Riel wrote:
On 05/28/2014 08:16 AM, Raghavendra K T wrote:
This patch looks very promising.
Thank you Rik.
[...]
- My kernbench/ebizzy test on baremetal (32 cpu +ht sandybridge) did not seem to
show the impact of extra cmpxchg. but there should be effect
On 05/29/2014 12:16 PM, Peter Zijlstra wrote:
On Wed, May 28, 2014 at 05:46:39PM +0530, Raghavendra K T wrote:
In virtualized environment there are mainly three problems
related to spinlocks that affect performance.
1. LHP (lock holder preemption)
2. Lock Waiter Preemption (LWP)
3.
Il 29/05/2014 11:16, James Hogan ha scritto:
Currently this is the only asynchronous modification of guest registers,
therefore it is fixed by adjusting the implementations of the
kvm_set_c0_guest_cause(), kvm_clear_c0_guest_cause(), and
kvm_change_c0_guest_cause() macros which are used for
Hi Paolo,
On 29/05/14 11:36, Paolo Bonzini wrote:
Il 29/05/2014 11:16, James Hogan ha scritto:
Currently this is the only asynchronous modification of guest registers,
therefore it is fixed by adjusting the implementations of the
kvm_set_c0_guest_cause(), kvm_clear_c0_guest_cause(), and
Il 29/05/2014 12:55, James Hogan ha scritto:
Shouldn't you have a loop too around the ll/sc?
Yes, it has a do {} while () look around the inline asm, although I
didn't mention it in the commit message. It's modelled on
arch/mips/include/asm/bitops.h.
Ugh, sorry---I misread that as a
On Wed, May 28, 2014 at 4:14 AM, Jidong Xiao jidong.x...@gmail.com wrote:
Hi,
In kvm_set_msr_common(), I see that the follow piece of code will
handle the write operation to the register MSR_K7_HWCR.
case MSR_K7_HWCR:
data = ~(u64)0x40; /* ignore flush filter disable */
On 29/05/14 11:36, Paolo Bonzini wrote:
Il 29/05/2014 11:16, James Hogan ha scritto:
Here are a range of MIPS KVM TE fixes, preferably for v3.16 but I know
it's probably a bit late now. Changes are pretty minimal though since
v1 so please consider. They can also be found on my kvm_mips_queue
Il 29/05/2014 16:41, James Hogan ha scritto:
+
+/* If VM clock stopped then state was already saved when it was stopped */
+if (runstate_is_running()) {
+ret = kvm_mips_save_count(cs);
+if (ret 0) {
+return ret;
+}
+}
+
You're expecting that
Hi Paolo,
On 29/05/14 16:23, Paolo Bonzini wrote:
Il 29/05/2014 16:41, James Hogan ha scritto:
+
+/* If VM clock stopped then state was already saved when it was
stopped */
+if (runstate_is_running()) {
+ret = kvm_mips_save_count(cs);
+if (ret 0) {
+
Il 29/05/2014 18:27, James Hogan ha scritto:
(although as it stands CP0_Count never represents the offset from the VM
clock for KVM like it does with a running Count with TCG, so the vmstate
is technically incompatible between TCG/KVM).
That can be fixed in cpu_save/cpu_load hooks, like
So this needs to be cleared up given this is key to logging.
Cases this code handles during migration -
1. huge page fault described above - write protect fault so you breakup
the huge page.
2. All other faults - first time access, pte write protect you again wind up
in
Chris Webb ch...@arachsys.com wrote:
My CPU flags inside the crashing guest look like this:
fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36
clflush
mmx fxsr sse sse2 ht syscall nx mmxext fxsr_opt pdpe1gb lm rep_good nopl
extd_apicid pni pclmulqdq ssse3 fma cx16
Il 29/05/2014 19:45, Chris Webb ha scritto:
Chris Webb ch...@arachsys.com wrote:
My CPU flags inside the crashing guest look like this:
fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush
mmx fxsr sse sse2 ht syscall nx mmxext fxsr_opt pdpe1gb lm rep_good nopl
On Thu, May 29, 2014 at 10:08:07AM -0700, Mario Smarduch wrote:
So this needs to be cleared up given this is key to logging.
Cases this code handles during migration -
1. huge page fault described above - write protect fault so you breakup
the huge page.
2. All other faults - first
Paolo Bonzini pbonz...@redhat.com wrote:
Il 29/05/2014 19:45, Chris Webb ha scritto:
Chris Webb ch...@arachsys.com wrote:
My CPU flags inside the crashing guest look like this:
fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36
clflush
mmx fxsr sse sse2 ht syscall
On 05/29/2014 10:57 AM, Christoffer Dall wrote:
On Thu, May 29, 2014 at 10:08:07AM -0700, Mario Smarduch wrote:
So this needs to be cleared up given this is key to logging.
Cases this code handles during migration -
1. huge page fault described above - write protect fault so you breakup
From: Deng-Cheng Zhu dengcheng@imgtec.com
The memory alias support has been removed since a1f4d39500 (KVM: Remove
memory alias support). So remove unalias_gfn from the MIPS port.
Reviewed-by: James Hogan james.ho...@imgtec.com
Signed-off-by: Deng-Cheng Zhu dengcheng@imgtec.com
---
Il 29/05/2014 21:12, Deng-Cheng Zhu ha scritto:
kvm_mips.c | 5 -
1 file changed
Applied, thanks.
paolo
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On Tue, 2014-05-20 at 19:25 -0500, Kim Phillips wrote:
From: Kim Phillips kim.phill...@freescale.com
Needed by platform device drivers, such as the vfio-platform driver
later in series, in order to bypass the existing OF, ACPI, id_table and
name string matches, and successfully be able to be
Hi Paolo,
On 29/05/14 18:03, Paolo Bonzini wrote:
Also, perhaps this bit in kvm_mips_restore_count is unnecessary, and so
is env-count_save_time in general:
+/* find time to resume the saved timer at */
+now = get_clock();
+count_resume = now - (cpu_get_clock_at(now)
On 29.05.14 21:43, Alex Williamson wrote:
On Tue, 2014-05-20 at 19:25 -0500, Kim Phillips wrote:
From: Kim Phillips kim.phill...@freescale.com
Needed by platform device drivers, such as the vfio-platform driver
later in series, in order to bypass the existing OF, ACPI, id_table and
name
On 29.05.14 09:45, Michael Neuling wrote:
+/* Values for 2nd argument to H_SET_MODE */
+#define H_SET_MODE_RESOURCE_SET_CIABR1
+#define H_SET_MODE_RESOURCE_SET_DAWR2
+#define H_SET_MODE_RESOURCE_ADDR_TRANS_MODE3
+#define H_SET_MODE_RESOURCE_LE4
Much better, but
On Thu, 2014-05-29 at 23:27 +0200, Alexander Graf wrote:
On 29.05.14 09:45, Michael Neuling wrote:
+/* Values for 2nd argument to H_SET_MODE */
+#define H_SET_MODE_RESOURCE_SET_CIABR1
+#define H_SET_MODE_RESOURCE_SET_DAWR2
+#define H_SET_MODE_RESOURCE_ADDR_TRANS_MODE3
I am a bank director from Hong Kong, I want you to be my partner in a
business project of mutual benefit. Get back to me if interested.
Thank you,
Kong Hui.
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On 05/28/2014 08:16 AM, Raghavendra K T wrote:
TODO:
- we need an intelligent way to nullify the effect of batching for baremetal
(because extra cmpxchg is not required).
To do this, you will need to have 2 slightly different algorithms
depending on the paravirt_ticketlocks_enabled jump
From: Andi Kleen a...@linux.intel.com
To avoid various problems (like leaking counters) the PEBS
virtualization needs white listing per CPU model. Add state to the
x86_pmu for this and enable it for Silvermont.
Silvermont is currently the only CPU where it is safe
to virtualize PEBS, as it
PEBS is very useful (e.g. enabling the more cycles:pp event or
memory profiling) Unfortunately it didn't work in virtualization,
which is becoming more and more common.
This patch kit implements simple PEBS virtualization for KVM on Silvermont
CPUs. Silvermont does not have the leak problems that
From: Andi Kleen a...@linux.intel.com
PEBS (Precise Event Bases Sampling) profiling is very powerful,
allowing improved sampling precision and much additional information,
like address or TSX abort profiling. cycles:p and :pp uses PEBS.
This patch enables PEBS profiling in KVM guests.
PEBS
From: Andi Kleen a...@linux.intel.com
Currently perf unconditionally disables PEBS for guest.
Now that we have the infrastructure in place to handle
it we can allow it for KVM owned guest events. For
the perf needs to know that a event is owned by
a guest. Add a new state bit in the perf_event
From: Andi Kleen a...@linux.intel.com
With PEBS virtualization the PEBS record gets delivered to the guest,
but the host sees the PMI. This would normally result in a spurious
PEBS PMI that is ignored. But we need to inject the PMI into the guest,
so that the guest PMI handler can handle the PEBS
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Thanks Zhang and Venkateshwara, some more follow up questions below:)
1. Does -realtime mlock=on allocate all the memory upfront and keep it
for the VM, or does it just make sure the memory that is allocated
within the guest is not swapped out under host memory pressure?
2. I notice on a 4G
This adds support for the H_SET_MODE hcall. This hcall is a
multiplexer that has several functions, some of which are called
rarely, and some which are potentially called very frequently.
Here we add support for the functions that set the debug registers
CIABR (Completed Instruction Address
Am 29.05.2014 um 08:22 schrieb Michael Neuling mi...@neuling.org:
This adds support for the H_SET_MODE hcall. This hcall is a
multiplexer that has several functions, some of which are called
rarely, and some which are potentially called very frequently.
Here we add support for the
+/* Values for 2nd argument to H_SET_MODE */
+#define H_SET_MODE_RESOURCE_SET_CIABR1
+#define H_SET_MODE_RESOURCE_SET_DAWR2
+#define H_SET_MODE_RESOURCE_ADDR_TRANS_MODE3
+#define H_SET_MODE_RESOURCE_LE4
Much better, but I think you want to make use of
On Thu, 2014-05-29 at 23:27 +0200, Alexander Graf wrote:
On 29.05.14 09:45, Michael Neuling wrote:
+/* Values for 2nd argument to H_SET_MODE */
+#define H_SET_MODE_RESOURCE_SET_CIABR1
+#define H_SET_MODE_RESOURCE_SET_DAWR2
+#define H_SET_MODE_RESOURCE_ADDR_TRANS_MODE3
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