On 2014-06-16 18:56, Bandan Das wrote:
> Jan Kiszka writes:
>
>> SDM says bits 1, 4-6, 8, 13-16, and 26 have to be set.
>>
>> Signed-off-by: Jan Kiszka
>> ---
>> arch/x86/include/asm/vmx.h | 3 +++
>> arch/x86/kvm/vmx.c | 5 +++--
>> 2 files changed, 6 insertions(+), 2 deletions(-)
>>
>
On 2014-06-16 18:54, Bandan Das wrote:
> Jan Kiszka writes:
>
>> We already implemented them but failed to advertise them. Currently they
>> all return the identical values to the capability MSRs they are
>> augmenting. So there is no change in exposed features yet.
>>
>> Drop related comments at
On Tue, Jun 17, 2014 at 06:21:23AM +0200, Paolo Bonzini wrote:
> Il 16/06/2014 18:47, John Nielsen ha scritto:
> >On Jun 16, 2014, at 10:39 AM, Paolo Bonzini wrote:
> >
> >>Il 16/06/2014 18:09, John Nielsen ha scritto:
> >The only substantial difference on the hardware side is the CPU.
> >
On 2014-06-17 07:24, Paolo Bonzini wrote:
> Il 15/06/2014 08:20, Jan Kiszka ha scritto:
>>> > I think implementing Xen hypercalls in jailhouse for grant table and
>>> > event channels would actually make a lot of sense. The Xen
>>> > implementation is 2.5kLOC and I think it should be possible to c
Il 15/06/2014 08:20, Jan Kiszka ha scritto:
> I think implementing Xen hypercalls in jailhouse for grant table and
> event channels would actually make a lot of sense. The Xen
> implementation is 2.5kLOC and I think it should be possible to compact
> it noticeably, especially if you limit yourse
Il 16/06/2014 19:02, Bandan Das ha scritto:
> - vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
> + if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS) {
> + kvm_set_dr(vcpu, 7, vmcs12->guest_dr7);
> + vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_i
Il 16/06/2014 19:38, Bandan Das ha scritto:
Nadav Amit writes:
The emulator does not emulate the xadd instruction correctly if the two
operands are the same. In this (unlikely) situation the result should be the
sum of X and X (2X) when it is currently X. The solution is to first perform
wri
Il 16/06/2014 18:47, John Nielsen ha scritto:
On Jun 16, 2014, at 10:39 AM, Paolo Bonzini wrote:
Il 16/06/2014 18:09, John Nielsen ha scritto:
The only substantial difference on the hardware side is the CPU.
The hosts where the problem occurs use "Intel(R) Xeon(R) CPU
E5-2650 v2 @ 2.60GHz", w
On Fri, Jun 13, 2014 at 10:10 PM, Paolo Bonzini wrote:
> Il 13/06/2014 15:41, Vincent JARDIN ha scritto:
>> I do repeat this use case that you had removed because vhost-user does
>> not solve it yet:
>>
- ivshmem -> framework to be generic to have shared memory for many
use cases (HPC,
On Mon, Jun 16, 2014 at 03:27:19PM +0900, Minchan Kim wrote:
> Hi, Joonsoo
>
> On Mon, Jun 16, 2014 at 02:40:43PM +0900, Joonsoo Kim wrote:
> > We should free memory for bitmap when we find zone mis-match,
> > otherwise this memory will leak.
> >
> > Additionally, I copy code comment from PPC KVM
On Mon, Jun 16, 2014 at 11:11:35AM +0200, Marek Szyprowski wrote:
> Hello,
>
> On 2014-06-16 07:40, Joonsoo Kim wrote:
> >Currently, there are two users on CMA functionality, one is the DMA
> >subsystem and the other is the KVM on powerpc. They have their own code
> >to manage CMA reserved area ev
On Wed, Jun 11, 2014 at 12:33:50PM +0200, Alexander Graf wrote:
> On the exit path from the guest we check what type of interrupt we received
> if we received one. This means we're doing hardware access to the XICS
> interrupt
> controller.
>
> However, when running on a little endian system, thi
On Wed, Jun 11, 2014 at 12:33:46PM +0200, Alexander Graf wrote:
> >From assembly code we might not only have to explicitly BE access 64bit
> >values,
> but sometimes also 32bit ones. Add helpers that allow for easy use of
> lwzx/stwx
> in their respective byte-reverse or native form.
>
> Signed-
I am resending it as my original reply has some HTML code & hence
rejected by the mailing lists.
On 06/15/2014 08:47 AM, Peter Zijlstra wrote:
+#ifdef CONFIG_PARAVIRT_SPINLOCKS
+
+/*
+ * Write a comment about how all this works...
+ */
+
+#define _Q_LOCKED_SLOW (2U<< _Q_LOCKED_OFFSET)
+
+s
On 06/15/2014 08:47 AM, Peter Zijlstra wrote:
When we detect a hypervisor (!paravirt, see later patches), revert to
a simple test-and-set lock to avoid the horrors of queue preemption.
Signed-off-by: Peter Zijlstra
---
arch/x86/include/asm/qspinlock.h | 14 ++
include/asm-generi
On Sun, Jun 15, 2014 at 02:46:57PM +0200, Peter Zijlstra wrote:
> Since Waiman seems incapable of doing simple things; here's my take on the
> paravirt crap.
>
> The first few patches are taken from Waiman's latest series, but the virt
> support is completely new. Its primary aim is to not mess up
On Sun, Jun 15, 2014 at 02:46:58PM +0200, Peter Zijlstra wrote:
> From: Waiman Long
>
> This patch introduces a new generic queue spinlock implementation that
> can serve as an alternative to the default ticket spinlock. Compared
> with the ticket spinlock, this queue spinlock should be almost as
Nadav Amit writes:
> The emulator does not emulate the xadd instruction correctly if the two
> operands are the same. In this (unlikely) situation the result should be the
> sum of X and X (2X) when it is currently X. The solution is to first perform
> writeback to the source, before writing to
Jan Kiszka writes:
> From: Jan Kiszka
>
> Consistently make sure we are not affected by any compiler reordering
> when evaluating the current stage.
Should we prevent accidental calls to the variable directly by moving
get/set to vmx.c or a separate file in lib/x86 altogether ?
> Signed-off-
On 6/16/14, 5:56 PM, Paolo Bonzini wrote:
Il 16/06/2014 13:53, Nadav Amit ha scritto:
On 6/16/14, 2:09 PM, Paolo Bonzini wrote:
Il 16/06/2014 12:33, Nadav Amit ha scritto:
Do you get this if the input register has bit 31 set?
No. To be frank, the scenario may be considered a bit synthetic: t
Jan Kiszka writes:
...
> /* cpu-based controls */
> rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
> nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high);
> @@ -2409,11 +2422,17 @@ static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32
> msr_index, u64 *pdata)
>
Jan Kiszka writes:
> SDM says bits 1, 4-6, 8, 13-16, and 26 have to be set.
>
> Signed-off-by: Jan Kiszka
> ---
> arch/x86/include/asm/vmx.h | 3 +++
> arch/x86/kvm/vmx.c | 5 +++--
> 2 files changed, 6 insertions(+), 2 deletions(-)
>
> diff --git a/arch/x86/include/asm/vmx.h b/arch/x86
Jan Kiszka writes:
> We already implemented them but failed to advertise them. Currently they
> all return the identical values to the capability MSRs they are
> augmenting. So there is no change in exposed features yet.
>
> Drop related comments at this chance that are partially incorrect and
>
Il 16/06/2014 18:29, James Hogan ha scritto:
Rather than adding comments, we might as well force it to be always zero
and just write get_clock() to COUNT_RESUME.
Finally, having to serialize env->count_save_time makes harder to
support migration from TCG to KVM and back.
Yes, I'm not keen on t
On 30/05/14 08:57, Paolo Bonzini wrote:
> Il 29/05/2014 22:44, James Hogan ha scritto:
>> Yes, I agree with your analysis and had considered something like this,
>> although it doesn't particularly appeal to my sense of perfectionism :).
>
> I can see that. But I think the simplification of the c
=
KVM Forum 2014: Call For Participation
October 14-16, 2014 - Congress Centre Düsseldorf - Düsseldorf, Germany
(All submissions must be received before midnight July 27, 2014)
On Mon, Jun 16, 2014 at 04:25:26PM +0100, Will Deacon wrote:
> Ok, thanks. In which case, I think this is really a combined property of
> the SMMU and the interrupt controller, so we might need some extra code
> so that the SMMU can check that the interrupt controller for the device
> is also capab
On Mon, 2014-06-16 at 17:21 +0200, Joerg Roedel wrote:
> On Mon, Jun 16, 2014 at 04:13:29PM +0100, Will Deacon wrote:
> > MSIs look just like memory accesses made by the device, so the SMMU
> > will translate them to point at the GIC ITS (doorbell). The ITS then
> > has tables to work out how to ro
On Mon, Jun 16, 2014 at 04:25:28PM +0100, Alex Williamson wrote:
> On Mon, 2014-06-16 at 16:04 +0100, Will Deacon wrote:
> > On Thu, Jun 05, 2014 at 06:03:11PM +0100, Antonios Motakis wrote:
> > > The ARM SMMU supports the IOMMU_NOEXEC protection flag. Add the
> > > corresponding IOMMU capability.
On Mon, 2014-06-16 at 16:04 +0100, Will Deacon wrote:
> On Thu, Jun 05, 2014 at 06:03:11PM +0100, Antonios Motakis wrote:
> > The ARM SMMU supports the IOMMU_NOEXEC protection flag. Add the
> > corresponding IOMMU capability.
> >
> > Signed-off-by: Antonios Motakis
> > ---
> > drivers/iommu/arm-
On Mon, Jun 16, 2014 at 04:21:58PM +0100, Joerg Roedel wrote:
> On Mon, Jun 16, 2014 at 04:13:29PM +0100, Will Deacon wrote:
> > MSIs look just like memory accesses made by the device, so the SMMU
> > will translate them to point at the GIC ITS (doorbell). The ITS then
> > has tables to work out ho
On Mon, Jun 16, 2014 at 04:13:29PM +0100, Will Deacon wrote:
> MSIs look just like memory accesses made by the device, so the SMMU
> will translate them to point at the GIC ITS (doorbell). The ITS then
> has tables to work out how to route the MSI.
>
> So, if IOMMU_CAP_INTR_REMAP is simply suppose
Il 16/06/2014 13:59, Jan Kiszka ha scritto:
Changes in v2:
- reordering to avoid breaking the disabling of CR3 access interception
- express VMX_BASIC_TRUE_CTLS via bit-shift
- rename host_debugctl -> vmcs01_debugctl
Jan Kiszka (5):
KVM: nVMX: Advertise support for MSR_IA32_VMX_TRUE_*_CTLS
K
On Mon, Jun 16, 2014 at 03:53:44PM +0100, Joerg Roedel wrote:
> On Sun, Jun 08, 2014 at 12:31:29PM +0200, Christoffer Dall wrote:
> > On Thu, Jun 05, 2014 at 07:03:12PM +0200, Antonios Motakis wrote:
> > > With an ARM SMMU, interrupt remapping should always be safe from the
> > > SMMU's point of vi
On Thu, Jun 05, 2014 at 06:03:11PM +0100, Antonios Motakis wrote:
> The ARM SMMU supports the IOMMU_NOEXEC protection flag. Add the
> corresponding IOMMU capability.
>
> Signed-off-by: Antonios Motakis
> ---
> drivers/iommu/arm-smmu.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/d
On Thu, Jun 05, 2014 at 06:03:09PM +0100, Antonios Motakis wrote:
> Exposing the XN flag of the SMMU driver as IOMMU_NOEXEC instead of
> IOMMU_EXEC makes it enforceable, since for IOMMUs that don't support
> the XN flag pages will always be executable.
>
> Signed-off-by: Antonios Motakis
> ---
>
Il 16/06/2014 13:53, Nadav Amit ha scritto:
On 6/16/14, 2:09 PM, Paolo Bonzini wrote:
Il 16/06/2014 12:33, Nadav Amit ha scritto:
Do you get this if the input register has bit 31 set?
No. To be frank, the scenario may be considered a bit synthetic: the
guest assigns a value to a general-purpo
On Sun, Jun 08, 2014 at 12:31:29PM +0200, Christoffer Dall wrote:
> On Thu, Jun 05, 2014 at 07:03:12PM +0200, Antonios Motakis wrote:
> > With an ARM SMMU, interrupt remapping should always be safe from the
> > SMMU's point of view, as it is properly handled by the GIC.
> >
> > Signed-off-by: Anto
On 16.06.14 06:22, Aneesh Kumar K.V wrote:
Alexander Graf writes:
So far we've been able to successfully run HV KVM on big endian hosts, but
once you dive into little endian land things start to fall apart.
This patch set enables HV KVM for little endian hosts. This should be the
final piece
Many real CPUs get this wrong as well, but ours is totally off: bits 9:1
define the highest index value.
Signed-off-by: Jan Kiszka
---
arch/x86/kvm/vmx.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/x86/kvm/vmx.c b/arch/x86/kvm/vmx.c
index f20a5ee..eabd8d8 100644
---
We already have this control enabled by exposing a broken
MSR_IA32_VMX_PROCBASED_CTLS value. This will properly advertise our
capability once the value is fixed by clearing the right bits in
MSR_IA32_VMX_TRUE_PROCBASED_CTLS. We also have to ensure to test the
right value on L2 entry.
Signed-off-by
We already implemented them but failed to advertise them. Currently they
all return the identical values to the capability MSRs they are
augmenting. So there is no change in exposed features yet.
Drop related comments at this chance that are partially incorrect and
redundant anyway.
Signed-off-by
Allow L1 to "leak" its debug controls into L2, i.e. permit cleared
VM_{ENTRY_LOAD,EXIT_SAVE}_DEBUG_CONTROLS. This requires to manually
transfer the state of DR7 and IA32_DEBUGCTLMSR from L1 into L2 as both
run on different VMCS.
Signed-off-by: Jan Kiszka
---
arch/x86/kvm/vmx.c | 44 +
SDM says bits 1, 4-6, 8, 13-16, and 26 have to be set.
Signed-off-by: Jan Kiszka
---
arch/x86/include/asm/vmx.h | 3 +++
arch/x86/kvm/vmx.c | 5 +++--
2 files changed, 6 insertions(+), 2 deletions(-)
diff --git a/arch/x86/include/asm/vmx.h b/arch/x86/include/asm/vmx.h
index d989829..bcb
Changes in v2:
- reordering to avoid breaking the disabling of CR3 access interception
- express VMX_BASIC_TRUE_CTLS via bit-shift
- rename host_debugctl -> vmcs01_debugctl
Jan Kiszka (5):
KVM: nVMX: Advertise support for MSR_IA32_VMX_TRUE_*_CTLS
KVM: nVMX: Allow to disable CR3 access intercep
On 6/16/14, 2:09 PM, Paolo Bonzini wrote:
Il 16/06/2014 12:33, Nadav Amit ha scritto:
Do you get this if the input register has bit 31 set?
No. To be frank, the scenario may be considered a bit synthetic: the
guest assigns a value to a general-purpose register in 64-bit mode,
setting the high
Use struct kvm_cpu instead of struct kvm.
This change is req'd due to commit
8d770c4096cdf73e1b79e7395ef3a86aa2887077
(kvmtool: virtio: pass trapped vcpu to IO accessors).
Signed-off-by: Andreas Herrmann
---
tools/kvm/mips/include/kvm/kvm-cpu-arch.h |4 ++--
1 file changed, 2 insertions(+),
Il 16/06/2014 13:25, Jan Kiszka ha scritto:
>
> If you reorder the first three patches as 2 then 3 then 1, you do not
> need to temporarily break CR3 access interception. There is no
> conflict, just changes in the context. Does that look good to you?
Fine with me, but I guess I should adjust
On 2014-06-16 12:53, Paolo Bonzini wrote:
> Il 15/06/2014 16:24, Jan Kiszka ha scritto:
>> +++ b/x86/vmx_tests.c
>> @@ -820,8 +820,8 @@ static int iobmp_exit_handler()
>> #define INSN_ALWAYS_TRAP2
>> #define INSN_NEVER_TRAP3
>>
>> -#define FIELD_EXIT_QUAL0
>> -#define FIELD_IN
On 2014-06-16 13:02, Paolo Bonzini wrote:
> Il 15/06/2014 16:24, Jan Kiszka ha scritto:
>> From: Jan Kiszka
>>
>> This particularly checks the case when debug controls are not to be
>> loaded/saved on host-guest transitions.
>>
>> We have to fake results related to IA32_DEBUGCTL as support for thi
On 2014-06-16 13:00, Paolo Bonzini wrote:
> Il 15/06/2014 16:24, Jan Kiszka ha scritto:
>> +for (n = 0; n < ARRAY_SIZE(vmx_ctl_msr); n++) {
>> +val = rdmsr(vmx_ctl_msr[n].index);
>> +default1 = vmx_ctl_msr[n].default1;
>> +ok = (val & default1) == default1 &&
>> +
On 2014-06-16 12:44, Paolo Bonzini wrote:
> Il 15/06/2014 16:18, Jan Kiszka ha scritto:
>> Nothing critical, but it further improves emulation accuracy,
>> specifically helpful when analyzing guest bugs...
>>
>> Corresponding kvm-unit-tests will be provided.
>>
>> Jan Kiszka (5):
>> KVM: nVMX: Fi
Il 16/06/2014 12:33, Nadav Amit ha scritto:
Do you get this if the input register has bit 31 set?
No. To be frank, the scenario may be considered a bit synthetic: the
guest assigns a value to a general-purpose register in 64-bit mode,
setting the high 32-bits to some non-zero value. Then, later
Il 15/06/2014 16:24, Jan Kiszka ha scritto:
The tests corresponding to (and going beyond) the issues fixed in
http://thread.gmane.org/gmane.comp.emulators.kvm.devel/123282
Jan Kiszka (5):
VMX: Add tests for CR3 and CR8 interception
VMX: Only use get_stage accessor
VMX: Test both intercepti
Il 15/06/2014 16:24, Jan Kiszka ha scritto:
> From: Jan Kiszka
>
> This particularly checks the case when debug controls are not to be
> loaded/saved on host-guest transitions.
>
> We have to fake results related to IA32_DEBUGCTL as support for this MSR
> is missing KVM. The test already contain
Il 15/06/2014 16:24, Jan Kiszka ha scritto:
+ for (n = 0; n < ARRAY_SIZE(vmx_ctl_msr); n++) {
+ val = rdmsr(vmx_ctl_msr[n].index);
+ default1 = vmx_ctl_msr[n].default1;
+ ok = (val & default1) == default1 &&
+ u32)val) ^ (v
Il 15/06/2014 16:24, Jan Kiszka ha scritto:
+++ b/x86/vmx_tests.c
@@ -820,8 +820,8 @@ static int iobmp_exit_handler()
#define INSN_ALWAYS_TRAP 2
#define INSN_NEVER_TRAP3
-#define FIELD_EXIT_QUAL0
-#define FIELD_INSN_INFO1
+#define FIELD_EXI
Il 15/06/2014 16:18, Jan Kiszka ha scritto:
Nothing critical, but it further improves emulation accuracy,
specifically helpful when analyzing guest bugs...
Corresponding kvm-unit-tests will be provided.
Jan Kiszka (5):
KVM: nVMX: Fix returned value of MSR_IA32_VMX_PROCBASED_CTLS
KVM: nVMX:
Il 15/06/2014 16:18, Jan Kiszka ha scritto:
From: Jan Kiszka
Allow L1 to "leak" its debug controls into L2, i.e. permit cleared
VM_{ENTRY_LOAD,EXIT_SAVE}_DEBUG_CONTROLS. This requires to manually
transfer the state of DR7 and IA32_DEBUGCTLMSR from L1 into L2 as both
run on different VMCS.
Sign
On 6/16/14, 1:17 PM, Paolo Bonzini wrote:
Il 15/06/2014 15:13, Nadav Amit ha scritto:
From: Nadav Amit
When the guest sets DR6 and DR7, KVM asserts the high 32-bits are
clear, and
otherwise injects a #GP exception. This exception should only be
injected only
if running in long-mode.
Signed-of
Il 15/06/2014 15:12, Nadav Amit ha scritto:
This patch-set resolves several emulator bugs. Each fix is independent of the
others. The DR6/7 bug can occur during DR-access exit (regardless to
unrestricted mode, MMIO and SPT).
Thanks for reviewing the patches,
Nadav
Nadav Amit (6):
KVM: x86: b
Il 15/06/2014 15:13, Nadav Amit ha scritto:
From: Nadav Amit
When the guest sets DR6 and DR7, KVM asserts the high 32-bits are clear, and
otherwise injects a #GP exception. This exception should only be injected only
if running in long-mode.
Signed-off-by: Nadav Amit
---
arch/x86/kvm/x86.c |
Hello,
On 2014-06-16 07:40, Joonsoo Kim wrote:
Currently, there are two users on CMA functionality, one is the DMA
subsystem and the other is the KVM on powerpc. They have their own code
to manage CMA reserved area even if they looks really similar.
>From my guess, it is caused by some needs on
On Mon, Jun 16, 2014 at 09:46:02AM +0200, Andrew Jones wrote:
> On Sat, Jun 14, 2014 at 04:44:47PM +0200, Christoffer Dall wrote:
> > On Wed, Jun 11, 2014 at 04:01:15PM +0200, Andrew Jones wrote:
> > > This is a v5 of a series that introduces arm to kvm-unit-tests. First,
> > > it does some tidying
On Sat, Jun 14, 2014 at 04:44:47PM +0200, Christoffer Dall wrote:
> On Wed, Jun 11, 2014 at 04:01:15PM +0200, Andrew Jones wrote:
> > This is a v5 of a series that introduces arm to kvm-unit-tests. First,
> > it does some tidying up of the repo. Then, it adds support for device
> > trees (libfdt),
On Sat, Jun 14, 2014 at 04:16:53PM +0200, Christoffer Dall wrote:
> On Wed, Jun 11, 2014 at 04:01:30PM +0200, Andrew Jones wrote:
> > This is the initial drop of the arm test framework and a first test
> > that just checks that setup completed (a selftest). kvm isn't needed
> > to run this test unl
Hello, please CC kvm list too.
On Fri, Jun 13, 2014 at 11:29:06AM +0800, Tang Chen wrote:
> On 06/13/2014 11:23 AM, Tang Chen wrote:
> >Hi Gleb,
> >
> >I'm working on host's memory hotplug (not guest) recently. I met a problem
> >in kvm and I'll be very appreciate if you'd like to give some advice
Joonsoo Kim writes:
> On Sat, Jun 14, 2014 at 12:55:39PM +0530, Aneesh Kumar K.V wrote:
>> Joonsoo Kim writes:
>>
>> > Currently, there are two users on CMA functionality, one is the DMA
>> > subsystem and the other is the kvm on powerpc. They have their own code
>> > to manage CMA reserved are
Joonsoo Kim writes:
> On Sat, Jun 14, 2014 at 02:23:59PM +0530, Aneesh Kumar K.V wrote:
>> Joonsoo Kim writes:
>>
>> > Now, we have general CMA reserved area management framework,
>> > so use it for future maintainabilty. There is no functional change.
>> >
>> > Acked-by: Michal Nazarewicz
>>
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