[PATCH] KVM: x86: Pending interrupt may be delivered after INIT

We encountered a scenario in which after an INIT is delivered, a pending interrupt is delivered, although it was sent before the INIT. As the SDM states in section 10.4.7.1, the ISR and the IRR should be cleared after INIT as KVM does. This also means that pending interrupts should be cleared. T

Re: [PATCH] KVM: x86: fix TSC matching

On Tue, Jun 24, 2014 at 9:42 AM, Tomasz Grabiec wrote: > > I've observed kvmclock being marked as unstable on a modern > single-socket system with a stable TSC and qemu-1.6.2 or qemu-2.0.0. > > The culprit was failure in TSC matching because of overflow of > kvm_arch::nr_vcpus_matched_tsc in case

Re: [PATCH] KVM: x86: Pending interrupt may be delivered after INIT

On Mon, Jun 30, 2014 at 11:35:27AM +0300, Nadav Amit wrote: > We encountered a scenario in which after an INIT is delivered, a pending > interrupt is delivered, although it was sent before the INIT. As the SDM > states in section 10.4.7.1, the ISR and the IRR should be cleared after INIT > as > K

[PATCH] KVM: nSVM: Fix IOIO bitmap evaluation

From: Jan Kiszka First, kvm_read_guest returns 0 on success. And then we need to take the access size into account when testing the bitmap: intercept if any of bits corresponding to the access is set. Signed-off-by: Jan Kiszka --- This does not yet solve all IOIO issues, there are emulation-re

Re: [RFC PATCH 1/1] Move two pinned pages to non-movable node in kvm.

Hi Gleb, On 06/30/2014 02:00 PM, Gleb Natapov wrote: On Mon, Jun 30, 2014 at 09:45:32AM +0800, Tang Chen wrote: On 06/21/2014 04:39 AM, Marcelo Tosatti wrote: On Fri, Jun 20, 2014 at 05:31:46PM -0300, Marcelo Tosatti wrote: IIRC your shadow page pinning patch series support flushing of ptes b

[PATCH v2] KVM: x86: Pending interrupt may be delivered after INIT

We encountered a scenario in which after an INIT is delivered, a pending interrupt is delivered, although it was sent before the INIT. As the SDM states in section 10.4.7.1, the ISR and the IRR should be cleared after INIT as KVM does. This also means that pending interrupts should be cleared. T

[PATCH TRIVIAL] kvm: Correct kvm_multiple_exception's naming

From: Borislav Petkov While staring at kvm exception code in conjunction with the recent #DF splat, this function's name was bugging me because it clearly deals with multiple exceptionS(!) but it is missing the plural in the naming. Fix that so that I can sleep at night :-) Signed-off-by: Borisl

[PATCH] KVM: nSVM: Fix IOIO size reported on emulation

From: Jan Kiszka The access size of an in/ins is reported in dst_bytes, and that of out/outs in src_bytes. Signed-off-by: Jan Kiszka --- I'm seeing one more issue now: on emulation of "in (%dx),%eax", we leave to user space several times and check interception also several times after returnin

Re: [PATCH 2/2 v2] ARM: KVM: user_mem_abort: support stage 2 MMIO page mapping

On Thu, Jun 26, 2014 at 09:46:26AM +0100, Will Deacon wrote: > On Thu, Jun 26, 2014 at 01:45:51AM +0100, Kim Phillips wrote: > > From: Kim Phillips > > > > A userspace process can map device MMIO memory via VFIO or /dev/mem, > > e.g., for platform device passthrough support in QEMU. > > > > Duri

Re: [PATCH 2/2 v2] ARM: KVM: user_mem_abort: support stage 2 MMIO page mapping

On 30/06/14 10:08, Christoffer Dall wrote: > On Thu, Jun 26, 2014 at 09:46:26AM +0100, Will Deacon wrote: >> On Thu, Jun 26, 2014 at 01:45:51AM +0100, Kim Phillips wrote: >>> From: Kim Phillips >>> >>> A userspace process can map device MMIO memory via VFIO or /dev/mem, >>> e.g., for platform devi

Re: [PATCH 1/2] KVM: device: add simple registration mechanism for kvm_device_ops

On Thu, 26 Jun 2014 18:30:16 +0100 Will Deacon wrote: > kvm_ioctl_create_device currently has knowledge of all the device types > and their associated ops. This is fairly inflexible when adding support > for new in-kernel device emulations, so move what we currently have out > into a table, which

nSVM: interception checks on emulation (was: [PATCH] KVM: nSVM: Fix IOIO size reported on emulation)

On 2014-06-30 11:07, Jan Kiszka wrote: > I'm seeing one more issue now: on emulation of "in (%dx),%eax", we leave > to user space several times and check interception also several times Correction: we only leave once for user space. > after returning. We use dx to calculate the port number for th

Re: [PATCH 1/2] KVM: device: add simple registration mechanism for kvm_device_ops

Hello, On Mon, Jun 30, 2014 at 10:21:14AM +0100, Cornelia Huck wrote: > On Thu, 26 Jun 2014 18:30:16 +0100 > Will Deacon wrote: > > > kvm_ioctl_create_device currently has knowledge of all the device types > > and their associated ops. This is fairly inflexible when adding support > > for new in

Re: [Qemu-devel] [questions] about KVM as a Microsoft-compatible hypervisor

On Mon, 2014-06-30 at 09:39 +0800, Zhang Haoyu wrote: > Hi, Vadim > I read the kvm-2012-forum paper < KVM as a Microsoft-compatible hypervisor>, > Any update and other references, please? > > Thanks, > Zhang Haoyu > > Unfortunately, not too much. >From the the most recent, we have lazy eoi imp

Re: [Qemu-devel] [questions] about KVM as a Microsoft-compatible hypervisor

On Mon, Jun 30, 2014 at 6:02 AM, Vadim Rozenfeld wrote: > On Mon, 2014-06-30 at 09:39 +0800, Zhang Haoyu wrote: >> Hi, Vadim >> I read the kvm-2012-forum paper < KVM as a Microsoft-compatible hypervisor>, >> Any update and other references, please? >> >> Thanks, >> Zhang Haoyu >> >> > > Unfortunat

Re: [PATCH 1/2] KVM: device: add simple registration mechanism for kvm_device_ops

On Mon, 30 Jun 2014 10:36:19 +0100 Will Deacon wrote: > Hello, > > On Mon, Jun 30, 2014 at 10:21:14AM +0100, Cornelia Huck wrote: > > On Thu, 26 Jun 2014 18:30:16 +0100 > > Will Deacon wrote: > > > diff --git a/include/uapi/linux/kvm.h b/include/uapi/linux/kvm.h > > > index e11d8f170a62..3b368

Re: [PATCH 1/2] KVM: device: add simple registration mechanism for kvm_device_ops

On Mon, Jun 30, 2014 at 11:25:01AM +0100, Cornelia Huck wrote: > On Mon, 30 Jun 2014 10:36:19 +0100 > Will Deacon wrote: > > On Mon, Jun 30, 2014 at 10:21:14AM +0100, Cornelia Huck wrote: > > > On Thu, 26 Jun 2014 18:30:16 +0100 > > > Will Deacon wrote: > > > > diff --git a/include/uapi/linux/kvm

[PATCH 1/6] KVM: Don't keep reference to irq routing table in irqfd struct

This makes the irqfd code keep a copy of the irq routing table entry for each irqfd, rather than a reference to the copy in the actual irq routing table maintained in kvm/virt/irqchip.c. This will enable us to change the routing table structure in future, or even not have a routing table at all on

[PATCH 5/6] KVM: Give IRQFD its own separate enabling Kconfig option

Currently, the IRQFD code is conditional on CONFIG_HAVE_KVM_IRQ_ROUTING. So that we can have the IRQFD code compiled in without having the IRQ routing code, this creates a new CONFIG_HAVE_KVM_IRQFD, makes the IRQFD code conditional on it instead of CONFIG_HAVE_KVM_IRQ_ROUTING, and makes all the pla

[PATCH 4/6] KVM: Move irq notifier implementation into eventfd.c

This moves the functions kvm_irq_has_notifier(), kvm_notify_acked_irq(), kvm_register_irq_ack_notifier() and kvm_unregister_irq_ack_notifier() from irqchip.c to eventfd.c. The reason for doing this is that those functions are used in connection with IRQFDs, which are implemented in eventfd.c. In

[PATCH 0/6] IRQFD without IRQ routing, enabled for XICS

This series of patches provides a way to implement IRQFD support without having to implement IRQ routing, and adds IRQFD support for the XICS interrupt controller emulation. (XICS is the interrupt controller defined for the pSeries machine type, used on IBM POWER servers). The basic approach is t

[PATCH 2/6] KVM: irqchip: Provide and use accessors for irq routing table

This provides accessor functions for the KVM interrupt mappings, in order to reduce the amount of code that accesses the fields of the kvm_irq_routing_table struct, and restrict that code to one file, virt/kvm/irqchip.c. The new functions are kvm_irq_map_gsi(), which maps from a global interrupt n

[PATCH 3/6] KVM: Move all accesses to kvm::irq_routing into irqchip.c

Now that struct _irqfd does not keep a reference to storage pointed to by the irq_routing field of struct kvm, we can move the statement that updates it out from under the irqfds.lock and put it in kvm_set_irq_routing() instead. That means we then have to take a srcu_read_lock on kvm->irq_srcu aro

[PATCH 6/6] KVM: PPC: Enable IRQFD support for the XICS interrupt controller

This makes it possible to use IRQFDs on platforms that use the XICS interrupt controller. To do this we implement kvm_irq_map_gsi() and kvm_irq_map_chip_pin() in book3s_xics.c, so as to provide a 1-1 mapping between global interrupt numbers and XICS interrupt source numbers. For now, all interrupt

[PATCH] KVM: nSVM: Set correct port for IOIO interception evaluation

From: Jan Kiszka Obtaining the port number from DX is bogus as a) there are immediate port accesses and b) user space may have changed the register content while processing the PIO access. Forward the correct value from the instruction emulator instead. Signed-off-by: Jan Kiszka --- Valentine,

Re: [Qemu-devel] Why I advise against using ivshmem

Stefan Hajnoczi writes: > On Tue, Jun 17, 2014 at 11:44:11AM +0200, Paolo Bonzini wrote: >> Il 17/06/2014 11:03, David Marchand ha scritto: >> >>Unless someone steps up and maintains ivshmem, I think it should be >> >>deprecated and dropped from QEMU. >> > >> >Then I can maintain ivshmem for QEMU

Re: [PATCH 1/2] KVM: device: add simple registration mechanism for kvm_device_ops

On Fri, Jun 27, 2014 at 03:17:57PM +0100, Paolo Bonzini wrote: > Il 26/06/2014 19:30, Will Deacon ha scritto: > > kvm_ioctl_create_device currently has knowledge of all the device types > > and their associated ops. This is fairly inflexible when adding support > > for new in-kernel device emulatio

Re: [PATCH 1/2] KVM: device: add simple registration mechanism for kvm_device_ops

On Fri, 27 Jun 2014 16:17:57 +0200 Paolo Bonzini wrote: > Il 26/06/2014 19:30, Will Deacon ha scritto: > > kvm_ioctl_create_device currently has knowledge of all the device types > > and their associated ops. This is fairly inflexible when adding support > > for new in-kernel device emulations, s

Re: [PATCH 1/2] KVM: device: add simple registration mechanism for kvm_device_ops

On Mon, Jun 30, 2014 at 12:14:27PM +0100, Cornelia Huck wrote: > On Fri, 27 Jun 2014 16:17:57 +0200 > Paolo Bonzini wrote: > > > Il 26/06/2014 19:30, Will Deacon ha scritto: > > > kvm_ioctl_create_device currently has knowledge of all the device types > > > and their associated ops. This is fairl

Re: [Qemu-devel] [questions] about KVM as a Microsoft-compatible hypervisor

On Mon, 2014-06-30 at 06:19 -0400, Jidong Xiao wrote: > On Mon, Jun 30, 2014 at 6:02 AM, Vadim Rozenfeld wrote: > > On Mon, 2014-06-30 at 09:39 +0800, Zhang Haoyu wrote: > >> Hi, Vadim > >> I read the kvm-2012-forum paper < KVM as a Microsoft-compatible > >> hypervisor>, > >> Any update and other

Re: [PATCH] KVM: x86: fix TSC matching

Il 30/06/2014 10:43, Tomasz Grabiec ha scritto: ping. I was waiting for Marcelo to comment on this patch, but it looks good. Thanks for the detailed commit message. Paolo -- To unsubscribe from this list: send the line "unsubscribe kvm" in the body of a message to majord...@vger.kernel.org M

Re: Re: [Qemu-devel] [questions] about KVM as a Microsoft-compatiblehypervisor

>> Hi, Vadim >> I read the kvm-2012-forum paper < KVM as a Microsoft-compatible hypervisor>, >> Any update and other references, please? >> >> Thanks, >> Zhang Haoyu >> >> > >Unfortunately, not too much. >From the the most recent, we have lazy eoi implemented by >MST and reference time counter

[PATCH 3.12 057/181] MIPS: KVM: Allocate at least 16KB for exception handlers

From: James Hogan 3.12-stable review patch. If anyone has any objections, please let me know. === commit 7006e2dfda9adfa40251093604db76d7e44263b3 upstream. Each MIPS KVM guest has its own copy of the KVM exception vector. This contains the TLB refill exception handler at offset 0x

Re: [PATCH] KVM: x86: Fix lapic.c debug prints

Il 30/06/2014 03:03, Nadav Amit ha scritto: sipi_vector = apic->sipi_vector; -pr_debug("vcpu %d received sipi with vector # %x\n", +apic_debug("vcpu %d received sipi with vector # %x\n", Why don't we just use pr_debug all throughout ? I don't know. I just tried to m

Re: [Qemu-devel] [questions] about KVM as a Microsoft-compatiblehypervisor

On Mon, 2014-06-30 at 19:45 +0800, Zhang Haoyu wrote: > >> Hi, Vadim > >> I read the kvm-2012-forum paper < KVM as a Microsoft-compatible > >> hypervisor>, > >> Any update and other references, please? > >> > >> Thanks, > >> Zhang Haoyu > >> > >> > > > >Unfortunately, not too much. > >From the

Re: [PATCH 0/6] IRQFD without IRQ routing, enabled for XICS

On 30.06.14 12:51, Paul Mackerras wrote: This series of patches provides a way to implement IRQFD support without having to implement IRQ routing, and adds IRQFD support for the XICS interrupt controller emulation. (XICS is the interrupt controller defined for the pSeries machine type, used on

[PATCH] KVM: PPC: e500: Fix default tlb for victim hint

Tlb search operation used for victim hint relies on the default tlb set by the host. When hardware tablewalk support is enabled in the host, the default tlb is TLB1 which leads KVM to evict the bolted entry. Set and restore the default tlb when searching for victim hint. Signed-off-by: Mihai Caram

[PATCH] KVM: PPC: e500: Emulate power management control SPR

For FSL e6500 core the kernel uses power management SPR register (PWRMGTCR0) to enable idle power down for cores and devices by setting up the idle count period at boot time. With the host already controlling the power management configuration the guest could simply benefit from it, so emulate gues

IT-Service Desk Mail

Your password will expire in 4 days‏ Click Here to validate your e-mail. Thanks IT-Service Desk Exchange Email Help (OWA) -- To unsubscribe from this list: send the line "unsubscribe kvm" in the body of a message to majord...@vger.kernel.org More majordomo info at http

Re: [KVM] About releasing vcpu when closing vcpu fd

Hi, Currently as per the specs for cpu_hot(un)plug, ACPI GPE Block: IO ports 0xafe0-0xafe3 where each bit corresponds to each CPU. Currently, EJ0 method in acpi-dsdt-cpu-hotplu.dsl doesn't do anything. Method(CPEJ, 2, NotSerialized) { // _EJ0 method - eject callback Sleep(200)

[PATCH v6 04/21] arm64: boot protocol documentation update for GICv3

Linux has some requirements that must be satisfied in order to boot on a system built with a GICv3. Acked-by: Christoffer Dall Signed-off-by: Marc Zyngier --- Documentation/arm64/booting.txt | 8 1 file changed, 8 insertions(+) diff --git a/Documentation/arm64/booting.txt b/Documentat

[PATCH v6 15/21] KVM: ARM: vgic: revisit implementation of irqchip_in_kernel

So far, irqchip_in_kernel() was implemented by testing the value of vctrl_base, which worked fine with GICv2. With GICv3, this field is useless, as we're using system registers instead of a emmory mapped interface. To solve this, add a boolean flag indicating if the we're using a vgic or not. Rev

[PATCH v6 16/21] arm64: KVM: remove __kvm_hyp_code_{start,end} from hyp.S

We already have __hyp_text_{start,end} to express the boundaries of the HYP text section, and __kvm_hyp_code_{start,end} are getting in the way of a more modular world switch code. Just turn __kvm_hyp_code_{start,end} into #defines mapping the linker-emited symbols. Acked-by: Catalin Marinas Rev

[PATCH v6 09/21] KVM: ARM: vgic: abstract MISR decoding

Instead of directly dealing with the GICH_MISR bits, move the code to its own function and use a couple of public flags to represent the actual state. Acked-by: Catalin Marinas Reviewed-by: Christoffer Dall Signed-off-by: Marc Zyngier --- include/kvm/arm_vgic.h | 4 virt/kvm/arm/vgic.c

[PATCH v6 11/21] KVM: ARM: vgic: abstract VMCR access

Instead of directly messing with with the GICH_VMCR bits for the CPU interface save/restore code, add accessors that encode/decode the entire set of registers exposed by VMCR. Not the most efficient thing, but given that this code is only used by the save/restore code, performance is far from bein

[PATCH v6 19/21] KVM: ARM: vgic: add the GICv3 backend

Introduce the support code for emulating a GICv2 on top of GICv3 hardware. Acked-by: Catalin Marinas Signed-off-by: Marc Zyngier --- arch/arm64/include/asm/kvm_asm.h | 2 + arch/arm64/kvm/vgic-v3-switch.S | 29 + include/kvm/arm_vgic.h | 28 + virt/kvm/arm/vgic-v3.c

[PATCH v6 13/21] KVM: ARM: introduce vgic_params structure

Move all the data specific to a given GIC implementation into its own little structure. Acked-by: Catalin Marinas Reviewed-by: Christoffer Dall Signed-off-by: Marc Zyngier --- include/kvm/arm_vgic.h | 11 virt/kvm/arm/vgic.c| 70 --

[PATCH v6 21/21] arm64: KVM: vgic: enable GICv2 emulation on top on GICv3 hardware

Add the last missing bits that enable GICv2 emulation on top of GICv3 hardware. Signed-off-by: Marc Zyngier --- arch/arm64/include/asm/kvm_host.h | 7 +++ arch/arm64/kvm/Makefile | 2 ++ virt/kvm/arm/vgic.c | 1 + 3 files changed, 10 insertions(+) diff --git a/arch/a

[PATCH v6 20/21] arm64: KVM: vgic: add GICv3 world switch

Introduce the GICv3 world switch code used to save/restore the GICv3 context. Acked-by: Catalin Marinas Reviewed-by: Christoffer Dall Signed-off-by: Marc Zyngier --- arch/arm64/include/asm/kvm_asm.h | 2 + arch/arm64/kernel/asm-offsets.c | 8 ++ arch/arm64/kvm/vgic-v3-switch.S | 238

[PATCH v6 05/21] KVM: arm/arm64: vgic: move GICv2 registers to their own structure

In order to make way for the GICv3 registers, move the v2-specific registers to their own structure. Acked-by: Catalin Marinas Reviewed-by: Christoffer Dall Signed-off-by: Marc Zyngier --- arch/arm/kernel/asm-offsets.c | 14 +-- arch/arm/kvm/interrupts_head.S | 26 +-

[PATCH v6 17/21] arm64: KVM: split GICv2 world switch from hyp code

Move the GICv2 world switch code into its own file, and add the necessary indirection to the arm64 switch code. Also introduce a new type field to the vgic_params structure. Acked-by: Catalin Marinas Reviewed-by: Christoffer Dall Signed-off-by: Marc Zyngier --- arch/arm/include/asm/kvm_host.h

[PATCH v6 01/21] irqchip: ARM: GIC: Move some bits of GICv2 to a library-type file

A few GICv2 low-level function are actually very useful to GICv3, and it makes some sense to share them across the two drivers. They end-up in their own file, with an additional parameter used to ensure an optional synchronization (unused on GICv2). Cc: Thomas Gleixner Cc: Jason Cooper Acked-by:

[PATCH v6 18/21] arm64: KVM: move HCR_EL2.{IMO,FMO} manipulation into the vgic switch code

GICv3 requires the IMO and FMO bits to be tightly coupled with some of the interrupt controller's register switch. In order to have similar code paths, move the manipulation of these bits to the GICv2 switch code. Acked-by: Catalin Marinas Reviewed-by: Christoffer Dall Signed-off-by: Marc Zyngi

[PATCH v6 08/21] KVM: ARM: vgic: abstract EISR bitmap access

Move the GICH_EISR access to its own function. Acked-by: Catalin Marinas Reviewed-by: Christoffer Dall Signed-off-by: Marc Zyngier --- include/kvm/arm_vgic.h | 1 + virt/kvm/arm/vgic.c| 22 -- 2 files changed, 21 insertions(+), 2 deletions(-) diff --git a/include/kvm/

Re: [PATCH] KVM: SVM: Fix CPL export via SS.DPL

Il 29/06/2014 17:12, Jan Kiszka ha scritto: From: Jan Kiszka We import the CPL via SS.DPL since ae9fedc793. However, we fail to export it this way so far. This caused spurious guest crashes, e.g. of Linux when accessing the vmport from guest user space which triggered register saving/restoring

[PATCH v6 12/21] KVM: ARM: vgic: introduce vgic_enable

Move the code dealing with enabling the VGIC on to vgic_ops. Acked-by: Catalin Marinas Reviewed-by: Christoffer Dall Signed-off-by: Marc Zyngier --- include/kvm/arm_vgic.h | 1 + virt/kvm/arm/vgic.c| 29 + 2 files changed, 22 insertions(+), 8 deletions(-) diff

[PATCH v6 14/21] KVM: ARM: vgic: split GICv2 backend from the main vgic code

Brutally hack the innocent vgic code, and move the GICv2 specific code to its own file, using vgic_ops and vgic_params as a way to pass information between the two blocks. Acked-by: Catalin Marinas Reviewed-by: Christoffer Dall Signed-off-by: Marc Zyngier --- arch/arm/kvm/Makefile | 1 + a

[PATCH v6 02/21] irqchip: arm64: Initial support for GICv3

The Generic Interrupt Controller (version 3) offers services that are similar to GICv2, with a number of additional features: - Affinity routing based on the CPU MPIDR (ARE) - System register for the CPU interfaces (SRE) - Support for more that 8 CPUs - Locality-specific Peripheral Interrupts (LPIs

[PATCH v6 00/21] arm64: GICv3 support

GICv3 is the base for a new generation of interrupt controllers designed to overcome some of the most glaring limitations of GICv2. Some of the features are: - Support for more than 8 CPUs (a lot more...) - System registers for CPU interface access (instead of the memory mapped GICC, GICV, GICH)

[PATCH v6 10/21] KVM: ARM: vgic: move underflow handling to vgic_ops

Move the code dealing with LR underflow handling to its own functions, and make them accessible through vgic_ops. Acked-by: Catalin Marinas Reviewed-by: Christoffer Dall Signed-off-by: Marc Zyngier --- include/kvm/arm_vgic.h | 2 ++ virt/kvm/arm/vgic.c| 28 +--- 2

[PATCH v6 06/21] KVM: ARM: vgic: introduce vgic_ops and LR manipulation primitives

In order to split the various register manipulation from the main vgic code, introduce a vgic_ops structure, and start by abstracting the LR manipulation code with a couple of accessors. Reviewed-by: Christoffer Dall Signed-off-by: Marc Zyngier --- include/kvm/arm_vgic.h | 18 ++ virt/kvm/

[PATCH v6 07/21] KVM: ARM: vgic: abstract access to the ELRSR bitmap

Move the GICH_ELRSR access to its own functions, and add them to the vgic_ops structure. Acked-by: Catalin Marinas Reviewed-by: Christoffer Dall Signed-off-by: Marc Zyngier --- include/kvm/arm_vgic.h | 2 ++ virt/kvm/arm/vgic.c| 43 ++- 2 files chan

[PATCH v6 03/21] arm64: GICv3 device tree binding documentation

Add the necessary documentation to support GICv3. Cc: Thomas Gleixner Cc: Mark Rutland Acked-by: Catalin Marinas Acked-by: Rob Herring Acked-by: Christoffer Dall Signed-off-by: Marc Zyngier --- Documentation/devicetree/bindings/arm/gic-v3.txt | 79 1 file changed, 7

Re: [PATCH] KVM: SVM: Fix CPL export via SS.DPL

On 2014-06-30 17:01, Paolo Bonzini wrote: > Il 29/06/2014 17:12, Jan Kiszka ha scritto: >> From: Jan Kiszka >> >> We import the CPL via SS.DPL since ae9fedc793. However, we fail to >> export it this way so far. This caused spurious guest crashes, e.g. of >> Linux when accessing the vmport from gue

Re: [PATCH] KVM: nSVM: Fix IOIO bitmap evaluation

Il 30/06/2014 10:54, Jan Kiszka ha scritto: + SVM_IOIO_SIZE_SHIFT; gpa = svm->nested.vmcb_iopm + (port / 8); - bit = port % 8; - val = 0; + start_bit = port % 8; + iopm_len = (start_bit + size > 8) ? 2 : 1; + mask = (0xf >> (4 - size)) << sta

Re: [PATCH] KVM: nSVM: Fix IOIO bitmap evaluation

On 2014-06-30 17:08, Paolo Bonzini wrote: > Il 30/06/2014 10:54, Jan Kiszka ha scritto: >> +SVM_IOIO_SIZE_SHIFT; >> gpa = svm->nested.vmcb_iopm + (port / 8); >> -bit = port % 8; >> -val = 0; >> +start_bit = port % 8; >> +iopm_len = (start_bit + size > 8) ? 2 : 1; >>

Re: [PATCH] KVM: SVM: Fix CPL export via SS.DPL

On Mon, Jun 30, 2014 at 05:03:57PM +0200, Jan Kiszka wrote: > 15.5.1: > > "When examining segment attributes after a #VMEXIT: > [...] > • Retrieve the CPL from the CPL field in the VMCB, not from any segment > DPL." Heey, it is even documented! :-P -- Regards/Gruss, Boris. Sent from a fat

Re: [PATCH] KVM: SVM: Fix CPL export via SS.DPL

On Mon, Jun 30, 2014 at 05:15:44PM +0200, Borislav Petkov wrote: > On Mon, Jun 30, 2014 at 05:03:57PM +0200, Jan Kiszka wrote: > > 15.5.1: > > > > "When examining segment attributes after a #VMEXIT: > > [...] > > • Retrieve the CPL from the CPL field in the VMCB, not from any segment > > DPL." >

Re: [PATCH] KVM: SVM: Fix CPL export via SS.DPL

Il 30/06/2014 17:03, Jan Kiszka ha scritto: 15.5.1: "When examining segment attributes after a #VMEXIT: [...] • Retrieve the CPL from the CPL field in the VMCB, not from any segment DPL." It's only the fourth paragraph below the one I did read... Paolo -- To unsubscribe from this list: send t

[PATCH 6/6 v2] KVM: PPC: Book3E: Enable e6500 core

Now that AltiVec support is in place enable e6500 core. Signed-off-by: Mihai Caraman --- v2: - no changes arch/powerpc/kvm/e500mc.c | 10 ++ 1 file changed, 10 insertions(+) diff --git a/arch/powerpc/kvm/e500mc.c b/arch/powerpc/kvm/e500mc.c index c60b653..0bc9684 100644 --- a/arch/pow

[PATCH 5/6 v2] KVM: PPC: Book3E: Add ONE_REG AltiVec support

Add ONE_REG support for AltiVec on Book3E. Signed-off-by: Mihai Caraman --- v2: - add comment describing VCSR register representation in KVM vs kernel arch/powerpc/include/uapi/asm/kvm.h | 5 + arch/powerpc/kvm/booke.c| 34 ++ 2 files changed, 3

[PATCH 2/6 v2] KVM: PPC: Book3E: Refactor SPE/FP exit handling

SPE/FP/AltiVec interrupts share the same numbers. Refactor SPE/FP exit handling to accommodate AltiVec later on the same flow. Add kvmppc_supports_spe() to detect suport for the unit at runtime since it can be configured in the kernel but not featured on hardware and vice versa. Signed-off-by: Mi

[PATCH 4/6 v2] KVM: PPC: Book3E: Add AltiVec support

Add KVM Book3E AltiVec support. KVM Book3E FPU support gracefully reuse host infrastructure so follow the same approach for AltiVec. Signed-off-by: Mihai Caraman --- v2: - integrate Paul's FP/VMX/VSX changes arch/powerpc/kvm/booke.c | 67 ++-- 1 file

[PATCH 1/6 v2] KVM: PPC: Book3E: Use common defines for SPE/FP/AltiVec int numbers

Use common BOOKE_IRQPRIO and BOOKE_INTERRUPT defines for SPE/FP/AltiVec which share the same interrupt numbers. Signed-off-by: Mihai Caraman --- v2: - remove outdated definitions arch/powerpc/include/asm/kvm_asm.h| 8 arch/powerpc/kvm/booke.c | 17 +

Re: [PATCH v6 00/21] arm64: GICv3 support

Marc, On Mon, Jun 30, 2014 at 04:01:29PM +0100, Marc Zyngier wrote: > I now have received enough Reviewed-by from people familiar with the > architecture, and a number of Tested-by from actual implementors, > which (IMHO) makes ready for merging into 3.17 (Thomas, Jason: How do > you want to play

[PATCH 0/6 v2] KVM: PPC: Book3e: AltiVec support

Add KVM Book3E AltiVec support and enable e6500 core. Integrates Paul's FP/VMX/VSX changes that landed in kvm-ppc-queue in January and take into account feedback. Mihai Caraman (6): KVM: PPC: Book3E: Use common defines for SPE/FP/AltiVec int numbers KVM: PPC: Book3E: Refactor SPE/FP exit hand

Re: [PATCH v6 00/21] arm64: GICv3 support

Hi Jason, On 30/06/14 16:43, Jason Cooper wrote: > Marc, > > On Mon, Jun 30, 2014 at 04:01:29PM +0100, Marc Zyngier wrote: >> I now have received enough Reviewed-by from people familiar with the >> architecture, and a number of Tested-by from actual implementors, >> which (IMHO) makes ready for m

[PATCH 3/6 v2] KVM: PPC: Book3E: Increase FPU laziness

Increase FPU laziness by calling kvmppc_load_guest_fp() just before returning to guest instead of each sched in. Without this improvement an interrupt may also claim floting point corrupting guest state. Signed-off-by: Mihai Caraman --- v2: - remove fpu_active - add descriptive comments arch/

Re: [PATCH v6 04/21] arm64: boot protocol documentation update for GICv3

Hi Marc, On Mon, Jun 30, 2014 at 04:01:33PM +0100, Marc Zyngier wrote: > Linux has some requirements that must be satisfied in order to boot > on a system built with a GICv3. > > Acked-by: Christoffer Dall > Signed-off-by: Marc Zyngier FWIW: Acked-by: Mark Rutland Mark. > --- > Documentat

Re: [PATCH v6 03/21] arm64: GICv3 device tree binding documentation

Hi Marc, On Mon, Jun 30, 2014 at 04:01:32PM +0100, Marc Zyngier wrote: > Add the necessary documentation to support GICv3. > > Cc: Thomas Gleixner > Cc: Mark Rutland > Acked-by: Catalin Marinas > Acked-by: Rob Herring > Acked-by: Christoffer Dall > Signed-off-by: Marc Zyngier No-one's prep

Re: [RFC v2] ARM VM System Specification

On 6/11/14, 5:06 AM, Arnd Bergmann wrote: On Wednesday 11 June 2014 10:16:03 Paolo Bonzini wrote: If kernels actually do use the UEFI runtime services and have no need for direct access to an RTC when runing in a UEFI compliant system, then I agree with not specifying the hardware details. T

Re: [PATCH 1/2] KVM: device: add simple registration mechanism for kvm_device_ops

Il 30/06/2014 11:21, Cornelia Huck ha scritto: On Thu, 26 Jun 2014 18:30:16 +0100 Will Deacon wrote: kvm_ioctl_create_device currently has knowledge of all the device types and their associated ops. This is fairly inflexible when adding support for new in-kernel device emulations, so move what

Re: [PATCH 1/2] KVM: device: add simple registration mechanism for kvm_device_ops

On Mon, 30 Jun 2014 19:22:55 +0200 Paolo Bonzini wrote: > Il 30/06/2014 11:21, Cornelia Huck ha scritto: > > On Thu, 26 Jun 2014 18:30:16 +0100 > > Will Deacon wrote: > > > >> kvm_ioctl_create_device currently has knowledge of all the device types > >> and their associated ops. This is fairly in

Re: [PATCH 1/2] KVM: device: add simple registration mechanism for kvm_device_ops

On Mon, Jun 30, 2014 at 06:22:55PM +0100, Paolo Bonzini wrote: > Il 30/06/2014 11:21, Cornelia Huck ha scritto: > > On Thu, 26 Jun 2014 18:30:16 +0100 > > Will Deacon wrote: > >> diff --git a/include/uapi/linux/kvm.h b/include/uapi/linux/kvm.h > >> index e11d8f170a62..3b368166286f 100644 > >> ---

Re: [PATCH 1/2] KVM: device: add simple registration mechanism for kvm_device_ops

Il 30/06/2014 19:31, Will Deacon ha scritto: > It would let Will keep the simpler code with an array, and autogenerate > KVM_DEV_TYPE_MAX. Although this is uapi, so we may need to #define the symbols anyway to avoid breaking userspace #ifndef tests. What do you reckon; is this an ABI break? Y

Re: [PATCH] KVM: x86: fix TSC matching

On Mon, Jun 30, 2014 at 01:41:40PM +0200, Paolo Bonzini wrote: > Il 30/06/2014 10:43, Tomasz Grabiec ha scritto: > >ping. > > I was waiting for Marcelo to comment on this patch, but it looks > good. Thanks for the detailed commit message. > > Paolo Looks good. -- To unsubscribe from this list:

Re: [PATCH v6 02/21] irqchip: arm64: Initial support for GICv3

On Mon, Jun 30, 2014 at 04:01:31PM +0100, Marc Zyngier wrote: > The Generic Interrupt Controller (version 3) offers services that are > similar to GICv2, with a number of additional features: > - Affinity routing based on the CPU MPIDR (ARE) > - System register for the CPU interfaces (SRE) > - Supp

Re: [PATCH] KVM: x86: Fix lapic.c debug prints

Il 30/06/2014 19:39, Bandan Das ha scritto: Paolo Bonzini writes: Il 30/06/2014 03:03, Nadav Amit ha scritto: sipi_vector = apic->sipi_vector; -pr_debug("vcpu %d received sipi with vector # %x\n", +apic_debug("vcpu %d received sipi with vector # %x\n", Why don't w

Re: [PATCH] KVM: x86: Fix lapic.c debug prints

Paolo Bonzini writes: > Il 30/06/2014 19:39, Bandan Das ha scritto: >> Paolo Bonzini writes: >> >>> Il 30/06/2014 03:03, Nadav Amit ha scritto: >> >> sipi_vector = apic->sipi_vector; >> -pr_debug("vcpu %d received sipi with vector # %x\n", >> +apic_debug

Re: [PATCH] KVM: PPC: e500: Fix default tlb for victim hint

On Mon, 2014-06-30 at 15:54 +0300, Mihai Caraman wrote: > Tlb search operation used for victim hint relies on the default tlb set by the > host. When hardware tablewalk support is enabled in the host, the default tlb > is > TLB1 which leads KVM to evict the bolted entry. Set and restore the defaul

Re: [PATCH] KVM: PPC: e500: Emulate power management control SPR

On Mon, 2014-06-30 at 15:55 +0300, Mihai Caraman wrote: > For FSL e6500 core the kernel uses power management SPR register (PWRMGTCR0) > to enable idle power down for cores and devices by setting up the idle count > period at boot time. With the host already controlling the power management > confi

Re: [PATCH] KVM: x86: Fix lapic.c debug prints

Paolo Bonzini writes: > Il 30/06/2014 03:03, Nadav Amit ha scritto: sipi_vector = apic->sipi_vector; -pr_debug("vcpu %d received sipi with vector # %x\n", +apic_debug("vcpu %d received sipi with vector # %x\n", >>> >>> Why don't we just use pr_debug a

Re: [PATCH 2/2] KVM : powerpc/booke: Allow debug interrupt injection to guest

On Sun, 2014-06-29 at 23:38 -0500, Bhushan Bharat-R65777 wrote: > > > -Original Message- > > From: Wood Scott-B07421 > > Sent: Friday, June 27, 2014 11:53 PM > > To: Bhushan Bharat-R65777 > > Cc: ag...@suse.de; kvm-...@vger.kernel.org; kvm@vger.kernel.org > > Subject: Re: [PATCH 2/2] KVM :

Re: [RFC v2] ARM VM System Specification

On Mon, Jun 30, 2014 at 12:19:15PM -0400, Jon Masters wrote: > On 6/11/14, 5:06 AM, Arnd Bergmann wrote: > >On Wednesday 11 June 2014 10:16:03 Paolo Bonzini wrote: > >> > >>>If kernels actually do use the UEFI runtime services and have no need > >>>for direct access to an RTC when runing in a UEFI

Re: [patch 2/5] KVM: MMU: allow pinning spte translations (TDP-only)

On Fri, Jun 20, 2014 at 01:09:12PM +0300, Gleb Natapov wrote: > On Thu, Jun 19, 2014 at 04:22:57PM -0300, Marcelo Tosatti wrote: > > On Thu, Jun 19, 2014 at 10:21:16AM +0300, Gleb Natapov wrote: > > > On Wed, Jun 18, 2014 at 08:12:05PM -0300, mtosa...@redhat.com wrote: > > > > Allow vcpus to pin sp

Re: [patch 4/5] KVM: MMU: reload request from GET_DIRTY_LOG path

On Fri, Jun 20, 2014 at 01:46:10PM +0300, Gleb Natapov wrote: > On Thu, Jun 19, 2014 at 03:40:31PM -0300, Marcelo Tosatti wrote: > > On Thu, Jun 19, 2014 at 11:17:19AM +0300, Gleb Natapov wrote: > > > On Wed, Jun 18, 2014 at 08:12:07PM -0300, mtosa...@redhat.com wrote: > > > > Reload remote vcpus M

Re: [RFC v2] ARM VM System Specification

On 30 June 2014 21:46, Christoffer Dall wrote: > Seems like we should stick a note in there about being UEFI compatible > requires an RTC. We went this far before Peter raised the issue with > noone else realizing it, so it seems like a good idea to me. How about: = Guest OSes in the VM imag

Re: [RFC PATCH 2/6] arm/arm64: KVM: Rename irq_active to irq_queued

On Sun, Jun 22, 2014 at 12:25:02PM +0100, Marc Zyngier wrote: > On 2014-06-14 21:51, Christoffer Dall wrote: > >We have a special bitmap on the distributor struct to keep track > >of when > >level-triggered interrupts are queued on the list registers. This > >was > >named irq_active, which is conf

Re: [PATCH 0/6] IRQFD without IRQ routing, enabled for XICS

On Mon, Jun 30, 2014 at 02:43:56PM +0200, Alexander Graf wrote: > > On 30.06.14 12:51, Paul Mackerras wrote: > >This series of patches provides a way to implement IRQFD support > >without having to implement IRQ routing, and adds IRQFD support for > >the XICS interrupt controller emulation. (XICS

Re: [patch 2/5] KVM: MMU: allow pinning spte translations (TDP-only)

> > So it we take from it that translation should be present the same goes for > > accessed and dirty. If Andi can clarify this within Intel it would be great. > > Andi? There were some problems on really old CPUs with non dirty/accessed pages (P4 generation) with PEBS. But PEBS virtualization is

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