-Original Message-
From: kvm-ppc-ow...@vger.kernel.org [mailto:kvm-ppc-
ow...@vger.kernel.org] On Behalf Of mihai.cara...@freescale.com
Sent: Monday, July 21, 2014 4:23 PM
To: Alexander Graf; Wood Scott-B07421
Cc: kvm-...@vger.kernel.org; kvm@vger.kernel.org; linuxppc-
https://bugzilla.kernel.org/show_bug.cgi?id=81011
Bug ID: 81011
Summary: crashed on launching KVM with Juniper Simulator
Product: Virtualization
Version: unspecified
Kernel Version: 3.14.4
Hardware: i386
OS: Linux
From: Ulrich Obergfell uober...@redhat.com
In some cases we don't want hard lockup detection enabled by default.
An example is when running as a guest. Introduce
watchdog_enable_hardlockup_detector(bool)
allowing those cases to disable hard lockup detection. This must be
executed early by the
It's not recommended for KVM guests to enable hard lockup detection, as
false positives may be easily triggered by, for example, vcpu overcommit.
However any kernel compiled with HARDLOCKUP_DETECTOR that detects a PMU
on boot will by default enable hard lockup detection. This series gives
a kernel
From: Ulrich Obergfell uober...@redhat.com
This patch avoids printing the message 'enabled on all CPUs, ...'
multiple times. For example, the issue can occur in the following
scenario:
1) watchdog_nmi_enable() fails to enable PMU counters and sets
cpu0_err.
2) 'echo [0|1]
From: Ulrich Obergfell uober...@redhat.com
Use watchdog_enable_hardlockup_detector() to set hard lockup detection's
default value to false. It's risky to run this detection in a guest, as
false positives are easy to trigger, especially if the host is
overcommitted.
Signed-off-by: Ulrich
3.11.10.14 -stable review patch. If anyone has any objections, please let me
know.
--
From: James Hogan james.ho...@imgtec.com
commit c6c0a6637f9da54f9472144d44f71cf847f92e20 upstream.
The kfree() function already NULL checks the parameter so remove the
redundant NULL checks
Il 24/07/2014 12:13, Andrew Jones ha scritto:
The running kernel still has the ability to enable/disable at any
time with /proc/sys/kernel/nmi_watchdog us usual. However even
when the default has been overridden /proc/sys/kernel/nmi_watchdog
will initially show '1'. To truly turn it on one
Il 22/07/2014 18:19, Ethan Zhao ha scritto:
Use helper function instead of direct operation to pci device
flag when set device to assigned or deassigned.
Signed-off-by: Ethan Zhao ethan.z...@oracle.com
---
virt/kvm/assigned-dev.c |2 +-
virt/kvm/iommu.c|4 ++--
2 files
- Original Message -
From: Paolo Bonzini pbonz...@redhat.com
To: Andrew Jones drjo...@redhat.com, linux-ker...@vger.kernel.org,
kvm@vger.kernel.org
Cc: uober...@redhat.com, dzic...@redhat.com, a...@linux-foundation.org,
mi...@redhat.com
Sent: Thursday, July 24, 2014 12:46:11 PM
- Original Message -
From: Paolo Bonzini pbonz...@redhat.com
To: Ulrich Obergfell uober...@redhat.com
Cc: Andrew Jones drjo...@redhat.com, linux-ker...@vger.kernel.org,
kvm@vger.kernel.org, dzic...@redhat.com, a...@linux-foundation.org,
mi...@redhat.com
Sent: Thursday, July 24, 2014
Il 24/07/2014 13:44, Ulrich Obergfell ha scritto:
But this means that it is not possible to re-enable softlockup detection
only. I think that should be the effect of echo 0 + echo 1, if
hardlockup detection was disabled by either the command line or patch 3.
The idea was to give the user
- Original Message -
From: Paolo Bonzini pbonz...@redhat.com
To: Ulrich Obergfell uober...@redhat.com
Cc: Andrew Jones drjo...@redhat.com, linux-ker...@vger.kernel.org,
kvm@vger.kernel.org, dzic...@redhat.com, a...@linux-foundation.org,
mi...@redhat.com
Sent: Thursday, July 24, 2014
On Jul 18, 2014, at 12:38 AM, Marcelo Tosatti mtosa...@redhat.com wrote:
On Thu, Jul 17, 2014 at 08:18:03PM +0300, Nadav Amit wrote:
Small question if I may regarding kvm_mmu_pin_pages:
...
I understand that the current use-case is for pinning only few
pages. Yet, wouldn't it be better
On 23.07.14 18:06, Mihai Caraman wrote:
Read guest last instruction from kvmppc_get_last_inst() allowing the function
to fail in order to emulate again. On bookehv architecture search for
the physical address and kmap it, instead of using Load External PID (lwepx)
instruction. This fixes an
On 23.07.14 13:52, Xiao Guangrong wrote:
SPRN_SIER and SPRN_MMCR2 are doublely saved, particularly
SPRN_MMCR2 is oversaved with a incorrect value which comes
from SPRN_PMC5
Signed-off-by: Xiao Guangrong xiaoguangr...@linux.vnet.ibm.com
This patch is already in upstream:
On 21.07.14 07:53, Bharat Bhushan wrote:
SPRN_SPRG is used by debug interrupt handler, so this is required for
debug support.
Signed-off-by: Bharat Bhushan bharat.bhus...@freescale.com
---
v1-v2
- sprng9 is 64bit, not 32bit
Looks very reasonable, but is missing a ONE_REG interface to make
On 18.07.14 02:55, Scott Wood wrote:
On Thu, 2014-07-17 at 17:01 +0530, Bharat Bhushan wrote:
There are shadow registers like, GSPRG[0-3], GSRR0, GSRR1 etc on
BOOKE-HV and these shadow registers are guest accessible.
So these shadow registers needs to be updated on BOOKE-HV.
This patch adds
Hi Paul,
I also confirm your patch works fine on my ARM test environment. I was
able to run
- with irqchip without regression
- without irqchip (ie removing routing totally), just implementing
identity kvm_irq_map_gsi and kvm_irq_map_chip_pin and proper
kvm_set_irq. The overall integration
On Jul 24, 2014, at 9:09 PM, Alexander Graf ag...@suse.de wrote:
On 23.07.14 13:52, Xiao Guangrong wrote:
SPRN_SIER and SPRN_MMCR2 are doublely saved, particularly
SPRN_MMCR2 is oversaved with a incorrect value which comes
from SPRN_PMC5
Signed-off-by: Xiao Guangrong
The deadline is coming in three days!
Paolo
Il 16/06/2014 18:08, Paolo Bonzini ha scritto:
=
KVM Forum 2014: Call For Participation
October 14-16, 2014 - Congress Centre Düsseldorf - Düsseldorf, Germany
(All submissions must
This mail is from Administrator; we wish to bring to your notice the Condition
of your email account.
We have just noticed that you have exceeded your email Database limit of 500 MB
quota and your email IP is causing conflict because it is been accessed in
different server location. You need to
If the physical address of GICV isn't page-aligned, then we end up
creating a stage-2 mapping of the page containing it, which causes us to
map neighbouring memory locations directly into the guest.
As an example, consider a platform with GICV at physical 0x2c02f000
running a 64k-page host
On 24 July 2014 20:27, Will Deacon will.dea...@arm.com wrote:
If the physical address of GICV isn't page-aligned, then we end up
creating a stage-2 mapping of the page containing it, which causes us to
map neighbouring memory locations directly into the guest.
As an example, consider a
On Thu, Jul 24, 2014 at 08:47:23PM +0100, Peter Maydell wrote:
On 24 July 2014 20:27, Will Deacon will.dea...@arm.com wrote:
If the physical address of GICV isn't page-aligned, then we end up
creating a stage-2 mapping of the page containing it, which causes us to
map neighbouring memory
On 07/24/2014 02:47 PM, Peter Maydell wrote:
On 24 July 2014 20:27, Will Deacon will.dea...@arm.com wrote:
If the physical address of GICV isn't page-aligned, then we end up
creating a stage-2 mapping of the page containing it, which causes us to
map neighbouring memory locations directly
On 07/24/2014 02:55 PM, Will Deacon wrote:
On Thu, Jul 24, 2014 at 08:47:23PM +0100, Peter Maydell wrote:
On 24 July 2014 20:27, Will Deacon will.dea...@arm.com wrote:
If the physical address of GICV isn't page-aligned, then we end up
creating a stage-2 mapping of the page containing it,
On 24 July 2014 20:55, Will Deacon will.dea...@arm.com wrote:
Again, that can be solved by introduced Marc's attr for determining the
GICV offset within the 64k page. I don't think that's -stable material.
Agreed that we don't want to put Marc's patchset in -stable
(and that without it systems
Patch adds HYP interface for global VM TLB invalidation without address
parameter. Generic VM TLB flush calls ARMv7 arch defined TLB flush function.
Signed-off-by: Mario Smarduch m.smard...@samsung.com
---
arch/arm/include/asm/kvm_asm.h |1 +
arch/arm/include/asm/kvm_host.h |1 +
This patch adds support for dirty page logging so far tested only on ARMv7 HW,
and verified to compile on armv8, ia64, mips, ppc, s390 and compile and run on
x86_64.
Change from previous version:
- kvm_flush_remote_tlbs() has generic and architecture specific variants.
armv7 (later armv8) uses
This patch adds support for keeping track of VM dirty pages. As dirty page log
is retrieved, the pages that have been written are write protected again for
next write and log read.
The dirty log read function is generic for armv7 and x86, and arch specific
for arm64, ia64, mips, powerpc, s390.
Patch adds support for initial write protection VM memlsot. This patch series
assumes that huge PUDs will not be used in 2nd stage tables.
Signed-off-by: Mario Smarduch m.smard...@samsung.com
---
arch/arm/include/asm/kvm_host.h |1 +
arch/arm/include/asm/kvm_mmu.h| 20 ++
This patch adds support for handling 2nd stage page faults during migration,
it disables faulting in huge pages, and dissolves huge pages to page tables.
In case migration is canceled huge pages will be used again.
Signed-off-by: Mario Smarduch m.smard...@samsung.com
---
arch/arm/kvm/mmu.c |
We now support SPRG9 for guest, so also add a one reg interface for same
Note: Changes are in bookehv code only as we do not have SPRG9 on booke-pr.
Signed-off-by: Bharat Bhushan bharat.bhus...@freescale.com
---
arch/powerpc/include/uapi/asm/kvm.h | 1 +
arch/powerpc/kvm/e500mc.c | 22
On 25.07.14 07:51, Bharat Bhushan wrote:
We now support SPRG9 for guest, so also add a one reg interface for same
Note: Changes are in bookehv code only as we do not have SPRG9 on booke-pr.
Signed-off-by: Bharat Bhushan bharat.bhus...@freescale.com
Thanks, applied along with the SPRG9
-Original Message-
From: kvm-ppc-ow...@vger.kernel.org [mailto:kvm-ppc-
ow...@vger.kernel.org] On Behalf Of mihai.cara...@freescale.com
Sent: Monday, July 21, 2014 4:23 PM
To: Alexander Graf; Wood Scott-B07421
Cc: kvm-ppc@vger.kernel.org; k...@vger.kernel.org; linuxppc-
On 23.07.14 18:06, Mihai Caraman wrote:
Read guest last instruction from kvmppc_get_last_inst() allowing the function
to fail in order to emulate again. On bookehv architecture search for
the physical address and kmap it, instead of using Load External PID (lwepx)
instruction. This fixes an
On 21.07.14 07:53, Bharat Bhushan wrote:
SPRN_SPRG is used by debug interrupt handler, so this is required for
debug support.
Signed-off-by: Bharat Bhushan bharat.bhus...@freescale.com
---
v1-v2
- sprng9 is 64bit, not 32bit
Looks very reasonable, but is missing a ONE_REG interface to make
Hi Paul,
I also confirm your patch works fine on my ARM test environment. I was
able to run
- with irqchip without regression
- without irqchip (ie removing routing totally), just implementing
identity kvm_irq_map_gsi and kvm_irq_map_chip_pin and proper
kvm_set_irq. The overall integration
We now support SPRG9 for guest, so also add a one reg interface for same
Note: Changes are in bookehv code only as we do not have SPRG9 on booke-pr.
Signed-off-by: Bharat Bhushan bharat.bhus...@freescale.com
---
arch/powerpc/include/uapi/asm/kvm.h | 1 +
arch/powerpc/kvm/e500mc.c | 22
On 25.07.14 07:51, Bharat Bhushan wrote:
We now support SPRG9 for guest, so also add a one reg interface for same
Note: Changes are in bookehv code only as we do not have SPRG9 on booke-pr.
Signed-off-by: Bharat Bhushan bharat.bhus...@freescale.com
Thanks, applied along with the SPRG9
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