"Aneesh Kumar K.V" writes:
> Paul Mackerras writes:
>
>> The B (segment size) field in the RB operand for the tlbie
>> instruction is two bits, which we get from the top two bits of
>> the first doubleword of the HPT entry to be invalidated. These
>> bits go in bits 8 and 9 of the RB operand (b
Paul Mackerras writes:
> The B (segment size) field in the RB operand for the tlbie
> instruction is two bits, which we get from the top two bits of
> the first doubleword of the HPT entry to be invalidated. These
> bits go in bits 8 and 9 of the RB operand (bits 54 and 55 in IBM
> bit numbering
From: "Suresh E. Warrier"
This fixes some inaccuracies in the state machine for the virtualized
ICP when implementing the H_IPI hcall (Set_MFFR and related states):
1. The old code wipes out any pending interrupts when the new MFRR is
more favored than the CPPR but less favored than a pending
Testing with KSM active in the host showed occasional corruption of
guest memory. Typically a page that should have contained zeroes
would contain values that look like the contents of a user process
stack (values such as 0x_3fff__xxx).
Code inspection in kvmppc_h_protect revealed that th
From: "Suresh E. Warrier"
The kvmppc_vcore_blocked() code does not check for the wait condition
after putting the process on the wait queue. This means that it is
possible for an external interrupt to become pending, but the vcpu to
remain asleep until the next decrementer interrupt. The fix is
From: Mahesh Salgaonkar
When we get an HMI (hypervisor maintenance interrupt) while in a
guest, we see that guest enters into paused state. The reason is, in
kvmppc_handle_exit_hv it falls through default path and returns to
host instead of resuming guest. This causes guest to enter into
paused
The B (segment size) field in the RB operand for the tlbie
instruction is two bits, which we get from the top two bits of
the first doubleword of the HPT entry to be invalidated. These
bits go in bits 8 and 9 of the RB operand (bits 54 and 55 in IBM
bit numbering).
The compute_tlbie_rb() function
Here are fixes for five bugs which were found in the testing of our
PowerKVM product. The bugs range from guest performance issues to
guest crashes and memory corruption. Please apply.
Paul.
---
arch/powerpc/include/asm/kvm_book3s_64.h | 2 +-
arch/powerpc/kvm/book3s_hv.c | 22
On Thu, 30 Oct 2014 12:19:00 -0700
Mario Smarduch wrote:
> On 10/30/2014 05:14 AM, Cornelia Huck wrote:
> > On Wed, 22 Oct 2014 15:34:07 -0700
> > Mario Smarduch wrote:
> >
> >> This patch defines KVM_GENERIC_DIRTYLOG, and moves dirty log read function
> >> to it's own file virt/kvm/dirtylog.c.
https://bugzilla.kernel.org/show_bug.cgi?id=87591
Bug ID: 87591
Summary: Host will call trace when loading igbvf.
Product: Virtualization
Version: unspecified
Kernel Version: 3.18.0-rc2
Hardware: All
OS: Linux
https://bugzilla.kernel.org/show_bug.cgi?id=87591
--- Comment #1 from Zhou, Chao ---
the first bad commit is:
commit 6cd33649fa83d97ba7b66f1d871a360e867c5220
Author: Bjorn Helgaas
Date: Wed Aug 27 14:29:47 2014 -0600
PCI: Add pci_configure_device() during enumeration
Some platforms
On Sun, Nov 02, 2014 at 12:19:09PM +0200, Michael S. Tsirkin wrote:
> On Thu, Oct 23, 2014 at 11:02:43AM +0800, Chao Peng wrote:
> > Add AVX512 feature bits, register definition and corresponding
> > xsave/vmstate support.
> >
> > Signed-off-by: Chao Peng
>
> Thanks!
>
> As this was first poste
On Fri, 2014-10-31 at 16:36 +0100, Paolo Bonzini wrote:
> Thanks, applied the series at last.
Thanks.
cheers
--
To unsubscribe from this list: send the line "unsubscribe kvm" in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
On Sun, Nov 02, 2014 at 11:08:09PM +0800, Herbert Xu wrote:
> On Sun, Nov 02, 2014 at 11:06:13PM +0800, Amos Kong wrote:
> > On Fri, Oct 31, 2014 at 03:23:21PM +0800, Herbert Xu wrote:
> > > On Fri, Oct 31, 2014 at 10:28:00AM +1030, Rusty Russell wrote:
> > > > Herbert Xu writes:
> > > > > On Thu,
On Sun, Nov 02, 2014 at 11:06:13PM +0800, Amos Kong wrote:
> On Fri, Oct 31, 2014 at 03:23:21PM +0800, Herbert Xu wrote:
> > On Fri, Oct 31, 2014 at 10:28:00AM +1030, Rusty Russell wrote:
> > > Herbert Xu writes:
> > > > On Thu, Sep 18, 2014 at 08:37:45PM +0800, Amos Kong wrote:
> > > >> From: Rus
On Fri, Oct 31, 2014 at 03:23:21PM +0800, Herbert Xu wrote:
> On Fri, Oct 31, 2014 at 10:28:00AM +1030, Rusty Russell wrote:
> > Herbert Xu writes:
> > > On Thu, Sep 18, 2014 at 08:37:45PM +0800, Amos Kong wrote:
> > >> From: Rusty Russell
> > >>
> > >> The previous patch added one potential pro
On Thu, Oct 23, 2014 at 11:02:43AM +0800, Chao Peng wrote:
> Add AVX512 feature bits, register definition and corresponding
> xsave/vmstate support.
>
> Signed-off-by: Chao Peng
Thanks!
As this was first posted after soft freeze, please
resubmit after 2.2 is out.
See schedule http://wiki.qemu.
In x86, you cannot MOV-sreg to memory is either 16-bits or 64-bits. When
destination is registers, and the operand size is 32-bits, the high 16-bits in
modern CPUs is filled with zero.
In contrast, KVM may write to memory 32-bits on MOV-sreg. This patch fixes KVM
behavior, and sets the destinatio
Although Intel SDM mentions bit 63 is reserved, MOV to CR3 can have bit 63 set.
As Intel SDM states in section 4.10.4 "Invalidation of TLBs and
Paging-Structure Caches": " MOV to CR3. ... If CR4.PCIDE = 1 and bit 63 of the
instruction’s source operand is 0 ..."
In other words, bit 63 is not reserv
CMPS and SCAS instructions are evaluated in the wrong order. For reference (of
CMPS), see http://www.fermimn.gov.it/linux/quarta/x86/cmps.htm : "Note that the
direction of subtraction for CMPS is [SI] - [DI] or [ESI] - [EDI]. The left
operand (SI or ESI) is the source and the right operand (DI or
DR6[0:3] (previous breakpoint indications) are cleared when #DB is injected
during handle_exception, just as real hardware does. Similarily, handle_dr
should clear DR6[0:3].
Signed-off-by: Nadav Amit
---
arch/x86/kvm/vmx.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/x86/kvm/vmx.c b
Real-mode exceptions do not deliver error code. As can be seen in Intel SDM
volume 2, real-mode exceptions do not have parentheses, which indicate
error-code. To avoid significant changes of the code, the error code is
"removed" during exception queueing.
Signed-off-by: Nadav Amit
---
arch/x86/
SYSCALL emulation currently clears in 64-bit mode eflags according to
MSR_SYSCALL_MASK. However, on bare-metal eflags[1] which is fixed to one
cannot be cleared, even if MSR_SYSCALL_MASK masks the bit. This wrong behavior
may result in failed VM-entry, as VT disallows entry with eflags[1] cleared
Task-switch emulation checks the privilege level prior to performing the
task-switch. This check is incorrect in the case of task-gates, in which the
tss.dpl is ignored, and can cause superfluous exceptions. Moreover this check
is unnecassary, since the CPU checks the privilege levels prior to ex
Commit 7fe864dc942c ("KVM: x86: Emulator considers imm as memory operand")
marked VEX instructions as such in protected mode. VEX-prefix instructions are
not supported relevant on real-mode and VM86, but should cause #UD instead of
being decoded as LES/LDS.
Fix this behaviour to be consistent wit
The emulator mistakenly considers some of the immediate operands as memory
operands, performs memory read and uses the wrong data. By default, every
operand is marked as OP_MEM, so if it is not changed, memory read may be
wrongly emulated and the wrong value would be used. Consider for instance t
LGDT and LIDT emulation logic is almost identical. Merge the logic into a
single point to avoid redundancy. This will be used by the next patch that
will ensure the bases of the loaded GDTR and IDTR are canonical.
Signed-off-by: Nadav Amit
---
arch/x86/kvm/emulate.c | 27 +++-
When resetting the VCPU, the FPU should be reset as well (e.g., XCR0 state).
Call fx_init during reset as well.
Signed-off-by: Nadav Amit
---
arch/x86/kvm/x86.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c
index 773c17e..9b90ea7 100644
--- a/arch
When emulating LTR/LDTR/LGDT/LIDT, #GP should be injected if the base is
non-canonical. Otherwise, VM-entry will fail.
Signed-off-by: Nadav Amit
---
arch/x86/kvm/emulate.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/arch/x86/kvm/emulate.c b/arch/x86/kvm/emulate.c
index d6bea35..830
According to Intel SDM push of segment selectors is done in the following
manner: "if the operand size is 32-bits, either a zero-extended value is pushed
on the stack or the segment selector is written on the stack using a 16-bit
move. For the last case, all recent Core and Atom processors perform
Now that KVM injects #UD on "unhandlable" error, it makes better sense to
return such error on sysenter instead of directly injecting #UD to the guest.
This allows to track more easily the unhandlable cases the emulator does not
support.
Signed-off-by: Nadav Amit
---
arch/x86/kvm/emulate.c | 6 +
x86 debug registers hold a linear address. Therefore, breakpoints detection
should consider CS.base, and check whether instruction linear address equals
(CS.base + RIP). This patch introduces a function to evaluate RIP linear
address and uses it for breakpoints detection.
Signed-off-by: Nadav Amit
APIC base relocation is unsupported by KVM. If anyone uses it, the least should
be to report a warning in the hypervisor.
Note that KVM-unit-tests uses this feature for some reason, so running the
tests triggers the warning.
Signed-off-by: Nadav Amit
---
arch/x86/kvm/lapic.c | 4
1 file ch
Currently, the APIC logical map does not consider VCPUs whose local-apic is
software-disabled. However, NMIs, INIT, etc. should still be delivered to such
VCPUs. Therefore, the APIC mode should first be determined, and then the map,
considering all VCPUs should be constructed.
To address this iss
Commit 3b32004a66e9 ("KVM: x86: movnti minimum op size of 32-bit is not kept")
did not fully fix the minimum operand size of MONTI emulation. Still, MOVNTI
may be mistakenly performed using 16-bit opsize.
This patch add No16 flag to mark an instruction does not support 16-bits
operand size.
Signe
If the emulation ends in fault, eflags should not be updated. However, several
instruction emulations (actually all the fastops) currently update eflags, if
the fault was detected afterwards (e.g., #PF during writeback).
Signed-off-by: Nadav Amit
---
arch/x86/kvm/x86.c | 4 +++-
1 file changed,
It should clear B0-B3 and set BD.
Signed-off-by: Nadav Amit
---
arch/x86/kvm/emulate.c | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/arch/x86/kvm/emulate.c b/arch/x86/kvm/emulate.c
index efe7239..273c37e 100644
--- a/arch/x86/kvm/emulate.c
+++ b/arch/x86/kvm/emulate
This patch-set fixes various KVM bugs, mainly in the emulator. Each patch is
independent, except for patches 15-16 (which are intended to fix a single bug).
Patch 19 ist not a real fix for bug but improves the behavior of KVM when it
cannot handle a certain guest behavior.
Some previous fixes were
In one occassion, decode_modrm uses the rm field after it is extended with
REX.B to determine the addressing mode. Doing so causes it not to read the
offset for rip-relative addressing.
This patch uses the value after masking instead.
Signed-off-by: Nadav Amit
---
arch/x86/kvm/emulate.c | 2 +-
Linus,
The following changes since commit cac7f2429872d3733dc3f9915857b1691da2eb2f:
Linux 3.18-rc2 (2014-10-26 16:48:41 -0700)
are available in the git repository at:
git://git.kernel.org/pub/scm/virt/kvm/kvm.git tags/for-linus
for you to fetch changes up to a73896cb5bbdce672945745db822435
Hi Paolo,
On 14/11/2 下午2:50, Paolo Bonzini wrote:
On 01/11/2014 03:49, Wanpeng Li wrote:
This is also not enough. I see the warning in the below path during the
test:
kvm_arch_vcpu_ioctl_run
-> kvm_apic_accept_events
-> kvm_vcpu_reset
Hmm, better bypass the problem altogether:
diff --git a/a
The srcu read lock must be held while accessing memslots (e.g.
when using gfn_to_* functions), however, commit c24ae0dcd3e8
("kvm: x86: Unpin and remove kvm_arch->apic_access_page") call
gfn_to_page() in kvm_vcpu_reload_apic_access_page() w/o hold it in
vmx_vcpu_reset() path which leads to suspici
42 matches
Mail list logo
