On 05/12/2014 03:24, Konrad Rzeszutek Wilk wrote:
> We could do a simple thing - which is that the paravirt_enabled
> could have the value 1 for Xen and 2 for KVM. The assembler logic
> would be inverted and just check for 1. I am not going to attempt
> to write the assembler code :-)
Wouldn't X
On 05/12/2014 02:33, t...@tetrioncapital.com wrote:
> May I know how could I check CPU support list on KVM?
QEMU: qemu-kvm -cpu help|grep x86
(or "/usr/libexec/qemu-kvm -cpu help|grep x86" depending on your
distribution)
Libvirt: virsh cpu-models x86_64|sort
Paolo
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On 05/12/2014 02:15, Wanpeng Li wrote:
> Hi Paolo,
> On Thu, Dec 04, 2014 at 04:57:05PM +0100, Paolo Bonzini wrote:
>> These are all the patches needed to support XSAVES.
>>
>
> I think you miss to add your patch "kvm: x86: mask out XSAVES" to
> this patchset,
That one is already on kvm/next,
On Thu, Dec 04, 2014 at 02:59:48PM -0800, Andy Lutomirski wrote:
> This code in arch/x86/kernel/entry_32.S is wrong:
>
> #ifdef CONFIG_PARAVIRT
> /*
> * The kernel can't run on a non-flat stack if paravirt mode
> * is active. Rather than try to fixup the high bits of
> * ESP, b
On Fri, Dec 05, 2014 at 08:34:47AM +0800, Wanpeng Li wrote:
>Hi Paolo,
>On Thu, Dec 04, 2014 at 04:57:11PM +0100, Paolo Bonzini wrote:
>>- EAX=0Dh, ECX=1: output registers ECX/EDX are reserved.
>>
>>- EAX=0Dh, ECX>1: output register ECX bit 0 is clear for all the CPUID
>>leaves we support, because
Hi Paolo,
On Thu, Dec 04, 2014 at 04:57:05PM +0100, Paolo Bonzini wrote:
>These are all the patches needed to support XSAVES.
>
I think you miss to add your patch "kvm: x86: mask out XSAVES" to
this patchset, I test the whole patchset w/ that patch applied on
skylake-client machine, and it looks
May I know how could I check CPU support list on KVM?
Sent from my BlackBerry 10 smartphone.
Original Message
From: Paolo Bonzini
Sent: Thursday, 4 December, 2014 11:36 PM
To: t...@tetrioncapital.com; Yong Wang
Cc: kvm
Subject: Re: kvm ivy bridge support?
On 04/12/2014 14:56, t...@tetrionca
Hi Paolo,
On Thu, Dec 04, 2014 at 04:57:10PM +0100, Paolo Bonzini wrote:
>This is the size of the XSAVES area. This starts providing guest support
>for XSAVES (with no support yet for supervisor states, i.e. XSS == 0
>always in guests for now).
>
>Wanpeng Li suggested testing XSAVEC as well as XSA
Hi Paolo,
On Thu, Dec 04, 2014 at 04:57:11PM +0100, Paolo Bonzini wrote:
>- EAX=0Dh, ECX=1: output registers ECX/EDX are reserved.
>
>- EAX=0Dh, ECX>1: output register ECX bit 0 is clear for all the CPUID
>leaves we support, because variable "supported" comes from XCR0 and not
>XSS. Bits above 0 a
This code in arch/x86/kernel/entry_32.S is wrong:
#ifdef CONFIG_PARAVIRT
/*
* The kernel can't run on a non-flat stack if paravirt mode
* is active. Rather than try to fixup the high bits of
* ESP, bypass this code entirely. This may break DOSemu
* and/or Wine support in
2014-12-04 16:57+0100, Paolo Bonzini:
> From: Wanpeng Li
>
> Add vmcs12 support for xsaves.
>
> Signed-off-by: Wanpeng Li
> Signed-off-by: Paolo Bonzini
> ---
Reviewed-by: Radim Krčmář
> + case EXIT_REASON_XSAVES: case EXIT_REASON_XRSTORS:
> + /*
> + * This shou
2014-12-04 16:57+0100, Paolo Bonzini:
> From: Wanpeng Li
>
> Add logic to get/set the XSS model-specific register.
>
> Signed-off-by: Wanpeng Li
> Signed-off-by: Paolo Bonzini
> ---
Reviewed-by: Radim Krčmář
> @@ -2896,7 +2919,8 @@ static __init int setup_vmcs_config(struct vmcs_config
> *
2014-12-04 16:57+0100, Paolo Bonzini:
> From: Wanpeng Li
>
> Initialize the XSS exit bitmap. It is zero so there should be no XSAVES
> or XRSTORS exits.
>
> Signed-off-by: Wanpeng Li
> Signed-off-by: Paolo Bonzini
> ---
Reviewed-by: Radim Krčmář
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2014-12-04 16:57+0100, Paolo Bonzini:
> From: Wanpeng Li
>
> Add logic to get/set the XSS model-specific register.
>
> Signed-off-by: Wanpeng Li
> Signed-off-by: Paolo Bonzini
> ---
Reviewed-by: Radim Krčmář
> @@ -2896,7 +2919,8 @@ static __init int setup_vmcs_config(struct vmcs_config
> *
2014-12-04 16:57+0100, Paolo Bonzini:
> Userspace is expecting non-compacted format for KVM_GET_XSAVE, but
> struct xsave_struct might be using the compacted format. Convert
> in order to preserve userspace ABI.
>
> Likewise, userspace is passing non-compacted format for KVM_SET_XSAVE
> but the k
On 04/12/2014 17:34, Greg KH wrote:
> On Thu, Dec 04, 2014 at 04:57:06PM +0100, Paolo Bonzini wrote:
>> > get_xsave_addr is the API to access XSAVE states, and KVM would
>> > like to use it. Export it.
> Use it in what way?
As in patch 2/9, to avoid that upgrading to a newer processor breaks
us
On Thu, 4 Dec 2014 18:20:05 +0200
"Michael S. Tsirkin" wrote:
> On Tue, Dec 02, 2014 at 02:00:18PM +0100, Cornelia Huck wrote:
> > From: Thomas Huth
> >
> > Handle the virtio-ccw revision according to what the guest sets.
> > When revision 1 is selected, we have a virtio-1 standard device
> > w
2014-12-04 16:49+0100, Paolo Bonzini:
> On 04/12/2014 14:14, Radim Krčmář wrote:
> > 2014-12-04 19:11+0800, Wanpeng Li:
> >> The the value of EBX should represent the size of XCR0 related XSAVE
> >> area since IA32_XSS is not used currently.
> >
> > True, but 'supported' is not the state of XCR0,
On Thu, Dec 04, 2014 at 04:57:06PM +0100, Paolo Bonzini wrote:
> get_xsave_addr is the API to access XSAVE states, and KVM would
> like to use it. Export it.
Use it in what way?
> Cc: sta...@vger.kernel.org
Why is this a stable patch?
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On Tue, Dec 02, 2014 at 02:00:18PM +0100, Cornelia Huck wrote:
> From: Thomas Huth
>
> Handle the virtio-ccw revision according to what the guest sets.
> When revision 1 is selected, we have a virtio-1 standard device
> with byteswapping for the virtio rings.
>
> When a channel gets disabled, we
From: David Hildenbrand
The cpu address of a source cpu (responsible for an external irq) is only to
be stored if bit 6 of the ext irq code is set.
If bit 6 is not set, it is to be zeroed out.
The special external irq code used for virtio and pfault uses the cpu addr as a
parameter field. As bi
From: Jens Freimann
Instead of returning a possibly random or'ed together value, let's
always return -EFAULT if rc is set.
Signed-off-by: Jens Freimann
Reviewed-by: David Hildenbrand
Acked-by: Cornelia Huck
Signed-off-by: Christian Borntraeger
---
arch/s390/kvm/interrupt.c | 26
From: Jens Freimann
Currently we use a mixture of atomic/non-atomic bitops
and the local_int spin lock to protect the pending_irqs bitmap
and interrupt payload data.
We need to use atomic bitops for the pending_irqs bitmap everywhere
and in addition acquire the local_int lock where interrupt dat
nux/kernel/git/kvms390/linux into HEAD
(2014-12-03 15:20:11 +0100)
are available in the git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/kvms390/linux.git
tags/kvm-s390-next-20141204
for you to fetch changes up to 99e20009aeee47049900ac152d7a88d4f68697d3:
KVM: s390: clean
get_xsave_addr is the API to access XSAVE states, and KVM would
like to use it. Export it.
Cc: sta...@vger.kernel.org
Cc: x...@kernel.org
Cc: H. Peter Anvin
Acked-by: Thomas Gleixner
Signed-off-by: Paolo Bonzini
---
arch/x86/kernel/xsave.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/a
- EAX=0Dh, ECX=1: output registers ECX/EDX are reserved.
- EAX=0Dh, ECX>1: output register ECX bit 0 is clear for all the CPUID
leaves we support, because variable "supported" comes from XCR0 and not
XSS. Bits above 0 are reserved, so ECX is overall zero. Output register
EDX is reserved.
Source
This is the size of the XSAVES area. This starts providing guest support
for XSAVES (with no support yet for supervisor states, i.e. XSS == 0
always in guests for now).
Wanpeng Li suggested testing XSAVEC as well as XSAVES, since in practice
no real processor exists that only has one of them, and
Userspace is expecting non-compacted format for KVM_GET_XSAVE, but
struct xsave_struct might be using the compacted format. Convert
in order to preserve userspace ABI.
Likewise, userspace is passing non-compacted format for KVM_SET_XSAVE
but the kernel will pass it to XRSTORS, and we need to conv
From: Wanpeng Li
Expose the XSAVES feature to the guest if the kvm_x86_ops say it is
available.
Signed-off-by: Wanpeng Li
Signed-off-by: Paolo Bonzini
---
arch/x86/include/asm/kvm_host.h | 1 +
arch/x86/include/asm/vmx.h | 1 +
arch/x86/kvm/cpuid.c| 3 ++-
arch/x86/kvm/svm.c
For code that deals with cpuid, this makes things a bit more readable.
Signed-off-by: Paolo Bonzini
---
arch/x86/kvm/cpuid.c | 14 +++---
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c
index a4f5ac46226c..11f09a2b31a0 100644
---
These are all the patches needed to support XSAVES.
Paolo Bonzini (5):
x86: export get_xsave_addr
KVM: x86: support XSAVES usage in the host
KVM: x86: use F() macro throughout cpuid.c
KVM: cpuid: set CPUID(EAX=0xd,ECX=1).EBX correctly
KVM: cpuid: mask more bits in leaf 0xd and subleaves
From: Wanpeng Li
Initialize the XSS exit bitmap. It is zero so there should be no XSAVES
or XRSTORS exits.
Signed-off-by: Wanpeng Li
Signed-off-by: Paolo Bonzini
---
arch/x86/include/asm/vmx.h | 2 ++
arch/x86/include/uapi/asm/vmx.h | 6 +-
arch/x86/kvm/vmx.c | 21 +++
From: Wanpeng Li
Add vmcs12 support for xsaves.
Signed-off-by: Wanpeng Li
Signed-off-by: Paolo Bonzini
---
arch/x86/kvm/vmx.c | 23 ++-
1 file changed, 22 insertions(+), 1 deletion(-)
diff --git a/arch/x86/kvm/vmx.c b/arch/x86/kvm/vmx.c
index ad1153a725a2..9bcc871f0635 10
From: Wanpeng Li
Add logic to get/set the XSS model-specific register.
Signed-off-by: Wanpeng Li
Signed-off-by: Paolo Bonzini
---
arch/x86/include/asm/kvm_host.h | 1 +
arch/x86/kvm/vmx.c | 29 -
2 files changed, 29 insertions(+), 1 deletion(-)
diff
On 04/12/2014 14:14, Radim Krčmář wrote:
> 2014-12-04 19:11+0800, Wanpeng Li:
>> The section of CPUID(EAX=0xd, ECX=1) in the spec which commit
>> f5c2290cd01e (KVM: cpuid: mask more bits in leaf 0xd and subleaves)
>> mentioned is older than SDM.
>>
>> EBX: Bits 31-00: The size in bytes of the XSA
VGIC initialization currently happens in three phases:
(1) kvm_vgic_create() (triggered by userspace GIC creation)
(2) vgic_init_maps() (triggered by userspace GIC register read/write
requests, or from kvm_vgic_init() if not already run)
(3) kvm_vgic_init() (triggered by first VM run)
We w
Hi Feng,
On 12/03/2014 08:39 AM, Feng Wu wrote:
> This patch adds the kvm-vfio interface for VT-d Posted-Interrrupts.
> When guests updates MSI/MSI-x information for an assigned-device,
update
> QEMU will use KVM_DEV_VFIO_DEVICE_POSTING_IRQ attribute to setup
> IRTE for VT-d PI. This patch impleme
On 04/12/2014 14:56, t...@tetrioncapital.com wrote:
> Interesting, is it depending on KVM or libvirt on CPU support?
It has to be supported all the way up. KVM provides emulation, QEMU
provides command-line parsing, libvirt provides XML parsing,
virt-manager probably can read the info from libv
On 04/12/2014 12:11, Wanpeng Li wrote:
> SDM 30.3 VMWRITE
>
> ELSIF secondary source operand does not correspond to any VMCS field
>THEN VMfailValid(VMREAD/VMWRITE from/to unsupported VMCS component);
>
> We can't suppose L1 VMM expose MPX to L2 just if L0 support MPX. There
> will be VMfai
On 04/12/2014 12:11, Wanpeng Li wrote:
> Add nested virtualization support for xsaves.
>
> Signed-off-by: Wanpeng Li
> ---
> arch/x86/kvm/vmx.c | 17 -
> 1 file changed, 16 insertions(+), 1 deletion(-)
>
> diff --git a/arch/x86/kvm/vmx.c b/arch/x86/kvm/vmx.c
> index 6e3a448..e
Hi Feng,
On 12/03/2014 08:39 AM, Feng Wu wrote:
> This patch adds and documents a new attribute
> KVM_DEV_VFIO_DEVICE_POSTING_IRQ in KVM_DEV_VFIO_DEVICE group.
> This new attribute is used for VT-d Posted-Interrupts.
>
> When guest OS changes the interrupt configuration for an
> assigned device, s
On 04/12/2014 09:24, Wanpeng Li wrote:
> The section of CPUID(EAX=0xd, ECX=1) in the spec which commit
> f5c2290cd01e (KVM: cpuid: mask more bits in leaf 0xd and subleaves)
> mentioned is older than SDM.
>
> EBX: Bits 31-00: The size in bytes of the XSAVE area containing all
> states enabled
On 04/12/2014 09:24, Wanpeng Li wrote:
> XSAVEC also use the compacted format for the extended region
> of the XSAVE area. This patch fix it by caculate the size of
> XSAVEC extended region of XSAVE area as compact format.
>
> Signed-off-by: Wanpeng Li
> ---
> arch/x86/kvm/cpuid.c | 2 +-
> 1
Interesting, is it depending on KVM or libvirt on CPU support?
Sent from my BlackBerry 10 smartphone.
Original Message
From: Paolo Bonzini
Sent: Thursday, 4 December, 2014 9:54 PM
To: t...@tetrioncapital.com; Yong Wang
Cc: kvm
Subject: Re: kvm ivy bridge support?
On 04/12/2014 13:17, t...@t
On 04/12/2014 09:24, Wanpeng Li wrote:
> The section of CPUID(EAX=0xd, ECX=1) in the spec which commit
> f5c2290cd01e (KVM: cpuid: mask more bits in leaf 0xd and subleaves)
> mentioned is older than SDM.
>
> EBX: Bits 31-00: The size in bytes of the XSAVE area containing all
> states enabled
On 04/12/2014 13:17, t...@tetrioncapital.com wrote:
> Nothing really specific, when I use virt-manager, on CPU type it
> doesn't have Ivy Bridge selection, I just wondering why.
Either your virt-manager or your libvirt or your QEMU are too old.
Kernel 3.17 supports up to Broadwell.
Paolo
--
To
2014-12-04 14:43+0100, Paolo Bonzini:
> On 03/12/2014 19:45, Radim Krčmář wrote:
> > Btw, we don't care about crashers from userspace?
>
> We do, but they're taken care of by
>
> if (xstate_bv & ~kvm_supported_xcr0())
> return -EINVAL;
>
> in kvm_vcpu_ioct
On 25/11/2014 21:24, Thomas Gleixner wrote:
> On Tue, 25 Nov 2014, Rik van Riel wrote:
>> On 11/25/2014 12:21 PM, Marcelo Tosatti wrote:
>>> Since lapic timer handler only wakes up a simple waitqueue,
>>> it can be executed from hardirq context.
>>>
>>> Reduces average cyclictest latency by 3us.
On Tue, Nov 25, 2014 at 06:38:04PM +0100, Paolo Bonzini wrote:
>
>
> On 25/11/2014 18:21, Marcelo Tosatti wrote:
> > +
> > + if (r == HRTIMER_RESTART) {
> > + do {
> > + ret = hrtimer_start_expires(data, HRTIMER_MODE_ABS);
> > + if (ret == -ETIME)
>
On 03/12/2014 19:45, Radim Krčmář wrote:
> 2014-12-03 15:26+0100, Paolo Bonzini:
>>
>>
>> On 03/12/2014 15:23, Nadav Amit wrote:
>>> I think it is better just to replace the last line with:
>>>
>>> *(u64 *)(dest + XSAVE_HDR_OFFSET) = xsave->xsave_hdr.xstate_bv
>
> Yeah, or we can use this value
2014-12-04 19:11+0800, Wanpeng Li:
> XSAVEC also use the compacted format for the extended region
> of the XSAVE area. This patch fix it by caculate the size of
> XSAVEC extended region of XSAVE area as compact format.
(I'll believe as it makes sense, but SDM could mention that.)
> Signed-off-by:
2014-12-04 19:11+0800, Wanpeng Li:
> The section of CPUID(EAX=0xd, ECX=1) in the spec which commit
> f5c2290cd01e (KVM: cpuid: mask more bits in leaf 0xd and subleaves)
> mentioned is older than SDM.
>
> EBX: Bits 31-00: The size in bytes of the XSAVE area containing all
> states enabled by XCR0|I
On 12/04/2014 01:07 PM, Peter Maydell wrote:
> On 4 December 2014 at 12:01, Eric Auger wrote:
>> Here is the sequence:
>> 1) The VGIC early initialization is initiated in a machine init done
>> notifier. This notifier is registered in kvm_arm_gic_realize
>> (http://lists.gnu.org/archive/html/qemu-
Nothing really specific, when I use virt-manager, on CPU type it doesn't have
Ivy Bridge selection, I just wondering why.
Sent from my BlackBerry 10 smartphone.
Original Message
From: Yong Wang
Sent: Thursday, 4 December, 2014 7:30 PM
To: Thomas Lau
Cc: kvm
Subject: Re: kvm ivy bridge suppo
On 4 December 2014 at 12:01, Eric Auger wrote:
> Here is the sequence:
> 1) The VGIC early initialization is initiated in a machine init done
> notifier. This notifier is registered in kvm_arm_gic_realize
> (http://lists.gnu.org/archive/html/qemu-devel/2014-12/msg00220.html). It
> executes after v
On 12/04/2014 11:02 AM, Peter Maydell wrote:
> On 2 December 2014 at 17:54, Eric Auger wrote:
>> as soon as VFIO signaling is set up (the device IRQ index is linked to
>> an eventfd, the physical IRQ VFIO handler is installed and the physical
>> IRQ is enabled at interrupt controller level), virtu
The section of CPUID(EAX=0xd, ECX=1) in the spec which commit
f5c2290cd01e (KVM: cpuid: mask more bits in leaf 0xd and subleaves)
mentioned is older than SDM.
EBX: Bits 31-00: The size in bytes of the XSAVE area containing all
states enabled by XCR0|IA32_XSS.
The the value of EBX should represent
Add nested virtualization support for xsaves.
Signed-off-by: Wanpeng Li
---
arch/x86/kvm/vmx.c | 17 -
1 file changed, 16 insertions(+), 1 deletion(-)
diff --git a/arch/x86/kvm/vmx.c b/arch/x86/kvm/vmx.c
index 6e3a448..e5bc349 100644
--- a/arch/x86/kvm/vmx.c
+++ b/arch/x86/kvm/v
XSAVEC also use the compacted format for the extended region
of the XSAVE area. This patch fix it by caculate the size of
XSAVEC extended region of XSAVE area as compact format.
Signed-off-by: Wanpeng Li
---
v1 -> v2:
* use | (bitwise or) instead of II (logical or)
arch/x86/kvm/cpuid.c | 2 +-
SDM 30.3 VMWRITE
ELSIF secondary source operand does not correspond to any VMCS field
THEN VMfailValid(VMREAD/VMWRITE from/to unsupported VMCS component);
We can't suppose L1 VMM expose MPX to L2 just if L0 support MPX. There
will be VMfailValid if L0 doesn't support MPX and L1 expose MPX to L
On Thu, Dec 04, 2014 at 05:04:18PM +0800, Thomas Lau wrote:
> Hi,
>
> Does KVM support ivy bridge instruction?
Can you be more specific? Which ivybridge instructions do you care about?
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On Thu, Dec 04, 2014 at 10:48:00AM +0100, Eric Auger wrote:
> Since the advent of dynamic initialization of VGIC, this latter is
> initialized very late, on the first vcpu run. This initialization
> could be initiated much earlier by the user-space, as soon as it has
> set the requested dimensionin
Hi Christoffer
On 12/03/2014 11:45 AM, Christoffer Dall wrote:
> On Tue, Dec 02, 2014 at 06:27:31PM +0100, Eric Auger wrote:
>> Since the advent of dynamic initialization of VGIC, this latter is
>> initialized very late, on the first vcpu run. This initialization
>> could be initiated much earlier
Peter Lieven dlh.net> writes:
>
> Andre Przywara wrote:
> > Dave Young wrote:
> >> Hi,
> >>
> >> With today's git version (qemu-kvm), I got following message in
> >> kernel dmesg
> >>
> >> [168344.215605] kvm: 27289: cpu0 unhandled wrmsr: 0x198 data 0
> > Are you sure about that? 0x198 is an In
On 2 December 2014 at 17:54, Eric Auger wrote:
> as soon as VFIO signaling is set up (the device IRQ index is linked to
> an eventfd, the physical IRQ VFIO handler is installed and the physical
> IRQ is enabled at interrupt controller level), virtual IRQs are likely
> to be injected. With current
2014-12-03 18:00 GMT+03:00 Paolo Bonzini :
> Hi, I think the problem was already reported, but I haven't reproduced
> it yet (no machine with apicv).
I have reproduce it. But very strange. I don't disable apicv in
kvm_intel module. If i start freebsd 10.1 with 1Gb ram all works fine.
If i start i
Since the advent of dynamic initialization of VGIC, this latter is
initialized very late, on the first vcpu run. This initialization
could be initiated much earlier by the user-space, as soon as it has
set the requested dimensioning parameters: number of IRQs, number of
vCPUs, base addresses.
One
Since the advent of dynamic initialization of VGIC, this latter is
initialized very late, on the first vcpu run. This initialization
could be initiated much earlier by the user, as soon as it has
provided the requested dimensioning parameters:
- number of IRQs and number of vCPUs,
- DIST and CPU in
To be more explicit upon vgic initialization failure, -ENODEV is
returned by vgic_init_maps when no online vcpus can be found at
init.
Signed-off-by: Eric Auger
---
virt/kvm/arm/vgic.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/virt/kvm/arm/vgic.c b/virt/kvm/arm/vgic.c
i
Now that user-space can initiate VGIC initialization independently
on the first vcpu run, let's check the user-space does not attempt
to create a VCPU after this initialization.
Signed-off-by: Eric Auger
---
arch/arm/kvm/arm.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm/kvm
This patch prevents user-space from changing VGIC base addresses
if the vgic already is initialized.
Signed-off-by: Eric Auger
---
Documentation/virtual/kvm/devices/arm-vgic.txt | 2 ++
virt/kvm/arm/vgic.c| 3 +++
2 files changed, 5 insertions(+)
diff --git a/Documen
I would stick with reading changelog and save some trouble!
On Thu, Dec 4, 2014 at 5:19 PM, Zhang Haoyu wrote:
>>since they change the logic inside a function and never change
>>function name, it's hard to tell by using nm kvm.ko as it only shows
>>what function name included on kernel module.
>>
>since they change the logic inside a function and never change
>function name, it's hard to tell by using nm kvm.ko as it only shows
>what function name included on kernel module.
>
Yes,
if you have the source, you can directly check it.,
otherwise, decompile kvm.ko, because apic_clear_isr() is in
By the way, after I installed new version of kernel which have vapic
patch on, Win7 is running properly now. Thanks.
On Thu, Dec 4, 2014 at 4:37 PM, Thomas Lau wrote:
> since they change the logic inside a function and never change
> function name, it's hard to tell by using nm kvm.ko as it only
Hi,
Does KVM support ivy bridge instruction?
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Hi Nadav,
On 12/4/14, 4:30 PM, Nadav Amit wrote:
Wanpeng Li wrote:
XSAVEC also use the compacted format for the extended region
of the XSAVE area. This patch fix it by caculate the size of
XSAVEC extended region of XSAVE area as compact format.
Signed-off-by: Wanpeng Li
---
arch/x86/kvm/cpui
since they change the logic inside a function and never change
function name, it's hard to tell by using nm kvm.ko as it only shows
what function name included on kernel module.
On Thu, Dec 4, 2014 at 3:15 PM, Zhang Haoyu wrote:
>>Is this the correct function?
>>kvm_lapic_set_eoi
>>
> No, see the
On Thu, 2014-12-04 at 10:48 +0800, Thomas Lau wrote:
> what does vapic affect Windows 7 at all if I disable it? if it just a
> minor performance drop, I am fine with that.
>
It's good to have it turned on. But you definitely can drop it off.
> On Thu, Dec 4, 2014 at 10:06 AM, Zhang Haoyu wrote
Wanpeng Li wrote:
> XSAVEC also use the compacted format for the extended region
> of the XSAVE area. This patch fix it by caculate the size of
> XSAVEC extended region of XSAVE area as compact format.
>
> Signed-off-by: Wanpeng Li
> ---
> arch/x86/kvm/cpuid.c | 2 +-
> 1 file changed, 1 insert
XSAVEC also use the compacted format for the extended region
of the XSAVE area. This patch fix it by caculate the size of
XSAVEC extended region of XSAVE area as compact format.
Signed-off-by: Wanpeng Li
---
arch/x86/kvm/cpuid.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
SDM 30.3 VMWRITE
ELSIF secondary source operand does not correspond to any VMCS field
THEN VMfailValid(VMREAD/VMWRITE from/to unsupported VMCS component);
We can't suppose L1 VMM expose MPX to L2 just if L0 support MPX. There
will be VMfailValid if L0 doesn't support MPX and L1 expose MPX to
The section of CPUID(EAX=0xd, ECX=1) in the spec which commit
f5c2290cd01e (KVM: cpuid: mask more bits in leaf 0xd and subleaves)
mentioned is older than SDM.
EBX: Bits 31-00: The size in bytes of the XSAVE area containing all
states enabled by XCR0|IA32_XSS.
The the value of EBX should repres
Add nested virtualization support for xsaves.
Signed-off-by: Wanpeng Li
---
arch/x86/kvm/vmx.c | 17 -
1 file changed, 16 insertions(+), 1 deletion(-)
diff --git a/arch/x86/kvm/vmx.c b/arch/x86/kvm/vmx.c
index 6e3a448..e5bc349 100644
--- a/arch/x86/kvm/vmx.c
+++ b/arch/x86/kvm/v
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