Ping..
Hi, Paolo, could you please have a look at this patch ?
Thanks,
Wincy
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This patch enables ARMv8 dirty page logging support. Plugs ARMv8 into generic
layer through Kconfig symbol, and drops earlier ARM64 constraints to enable
logging at architecture layer. I applies cleanly on top patches series
posted Dec 15:
https://lists.cs.columbia.edu/pipermail/kvmarm/2014-Decembe
This patch adds support for handling 2nd stage page faults during migration,
it disables faulting in huge pages, and dissolves huge pages to normal pages.
In case migration is canceled huge pages are used again, if memory conditions
permit it. I applies cleanly on top patches series posted Dec 15:
On Thu, Jan 8, 2015 at 2:31 PM, Marcelo Tosatti wrote:
> On Tue, Jan 06, 2015 at 11:49:09AM -0800, Andy Lutomirski wrote:
>> On Tue, Jan 6, 2015 at 10:45 AM, Marcelo Tosatti wrote:
>> > On Tue, Jan 06, 2015 at 10:26:22AM -0800, Andy Lutomirski wrote:
>> >> On Tue, Jan 6, 2015 at 10:13 AM, Marcelo
On Tue, Jan 06, 2015 at 11:49:09AM -0800, Andy Lutomirski wrote:
> On Tue, Jan 6, 2015 at 10:45 AM, Marcelo Tosatti wrote:
> > On Tue, Jan 06, 2015 at 10:26:22AM -0800, Andy Lutomirski wrote:
> >> On Tue, Jan 6, 2015 at 10:13 AM, Marcelo Tosatti
> >> wrote:
> >> > On Tue, Jan 06, 2015 at 08:56:4
On 08/01/2015 18:41, Marcelo Tosatti wrote:
> Paolo?
>
> > And cover letter is a bit misleading: The condition does nothing to
> > guarantee TSC based __delay() loop. (Right now, __delay() = delay_tsc()
> > whenever the hardware has TSC, regardless of stability, thus always.)
>
> OK.
Yes, be
On Thu, Jan 08, 2015 at 11:59:06AM +, Marc Zyngier wrote:
> From: Steve Capper
>
> ptep_clear_flush_young_notify and pmdp_clear_flush_young_notify both
> call the notifiers *after* the pte/pmd has been made young.
>
On x86 on EPT without hardware access bit (!shadow_accessed_mask),
we'll tr
On Mon, Jan 05, 2015 at 07:12:36PM +0100, Radim Krcmar wrote:
> 2014-12-23 15:58-0500, Marcelo Tosatti:
> > For the hrtimer which emulates the tscdeadline timer in the guest,
> > add an option to advance expiration, and busy spin on VM-entry waiting
> > for the actual expiration time to elapse.
> >
Hi Scott,
On 07/01/15 18:16, Scott Wood wrote:
> On Wed, 2015-01-07 at 18:11 +, Andre Przywara wrote:
>> On 07/01/15 17:45, Scott Wood wrote:
>>> On Wed, 2015-01-07 at 10:55 +, Andre Przywara wrote:
Hi Scott,
thanks for looking at the patch.
On 06/01/15 20:52, Scot
On 01/08/2015 03:32 AM, Christoffer Dall wrote:
[...]
>> Not sure myself what's the vision for PUD support.
>>
>
> with 4-level paging on aarch64, we use PUDs but we haven't added any
> code to insert huge PUDs (only regular ones) on the stage-2 page tables,
> even if the host kernel happens to su
On 01/08/2015 03:32 AM, Christoffer Dall wrote:
> On Wed, Jan 07, 2015 at 07:01:10PM -0800, Mario Smarduch wrote:
>> On 01/07/2015 05:05 AM, Christoffer Dall wrote:
>>> On Sun, Dec 14, 2014 at 11:28:08PM -0800, Mario Smarduch wrote:
This patch adds the same support for PUD huge page as for PMD
On 01/08/2015 02:56 AM, Christoffer Dall wrote:
> On Wed, Jan 07, 2015 at 05:51:15PM -0800, Mario Smarduch wrote:
>> On 01/07/2015 04:47 AM, Christoffer Dall wrote:
>>> On Sun, Dec 14, 2014 at 11:28:07PM -0800, Mario Smarduch wrote:
This patch enables ARMv8 ditry page logging support. Plugs AR
On 01/08/2015 02:45 AM, Christoffer Dall wrote:
> On Wed, Jan 07, 2015 at 05:43:18PM -0800, Mario Smarduch wrote:
>> Hi Christoffer,
>> before going through your comments, I discovered that
>> in 3.18.0-rc2 - a generic __get_user_pages_fast()
>> was implemented, now ARM picks this up. This causes
On 08/01/2015 15:59, Radim Krčmář wrote:
> Emulation does not utilize the feature.
Indeed... nice :)
Applied to kvm/queue, thanks.
Paolo
> Signed-off-by: Radim Krčmář
> ---
> arch/x86/kvm/x86.c | 4 +---
> 1 file changed, 1 insertion(+), 3 deletions(-)
>
> diff --git a/arch/x86/kvm/x86.c b
On 8 January 2015 at 15:06, Marc Zyngier wrote:
> On 08/01/15 13:16, Peter Maydell wrote:
>>> ASID cached VIVT icaches are also VMID tagged. It is thus impossible for
>>> stale cache lines to come with a new page. And if by synchronizing the
>>> caches you obtain a different instruction stream, it
On 08/01/15 13:16, Peter Maydell wrote:
> On 8 January 2015 at 13:07, Marc Zyngier wrote:
>>> Can you remind me why it's OK not to flush the icache for an
>>> ASID tagged VIVT icache? Making this page coherent might actually
>>> be revealing a change in the instructions associated with the VA,
>>>
Emulation does not utilize the feature.
Signed-off-by: Radim Krčmář
---
arch/x86/kvm/x86.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c
index 933a373..ed879f1 100644
--- a/arch/x86/kvm/x86.c
+++ b/arch/x86/kvm/x86.c
@@ -2743,6 +27
On Thu, Jan 08, 2015 at 01:29:28PM +0100, Borislav Petkov wrote:
> Ok, dammit, it happened again:
Running -rc+ 2without your first two patches doesn't trigger it. Well,
I don't know what workload even triggered it, it used to happen during
system upgrade. I left the box without your patches to bui
On 8 January 2015 at 13:07, Marc Zyngier wrote:
>> Can you remind me why it's OK not to flush the icache for an
>> ASID tagged VIVT icache? Making this page coherent might actually
>> be revealing a change in the instructions associated with the VA,
>> mightn't it?
>
> ASID cached VIVT icaches are
Andrea, Rik, please review this patch.
Thanks in advance,
Paolo
On 08/01/2015 12:59, Marc Zyngier wrote:
> From: Steve Capper
>
> ptep_clear_flush_young_notify and pmdp_clear_flush_young_notify both
> call the notifiers *after* the pte/pmd has been made young.
>
> This can cause problems with
On 23/12/2014 00:39, Andy Lutomirski wrote:
The pvclock vdso code was too abstracted to understand easily and
excessively paranoid. Simplify it for a huge speedup.
This opens the door for additional simplifications, as the vdso no
longer accesses the pvti for any vcpu other than vcpu 0.
Before
On 08/01/15 12:30, Peter Maydell wrote:
> On 8 January 2015 at 11:59, Marc Zyngier wrote:
>> @@ -180,10 +177,32 @@ static inline void coherent_cache_guest_page(struct
>> kvm_vcpu *vcpu, hva_t hva,
>> *
>> * VIVT caches are tagged using both the ASID and the VMID and
>> doesn't
On 08/01/2015 13:15, Andrej Manduch wrote:
>>> >> -/* FIXME: this code should not know anything about vcpus */
> I don't want to sounds like I'm nitpicking. But I need to ask. Why is
> this comment removed?
Because the real point of the comment was that the code should not know
anything
On 8 January 2015 at 11:59, Marc Zyngier wrote:
> @@ -180,10 +177,32 @@ static inline void coherent_cache_guest_page(struct
> kvm_vcpu *vcpu, hva_t hva,
> *
> * VIVT caches are tagged using both the ASID and the VMID and doesn't
> * need any kind of flushing (DDI 0406C.
On Fri, Nov 07, 2014 at 03:58:18PM -0800, Andy Lutomirski wrote:
> diff --git a/arch/x86/kernel/entry_64.S b/arch/x86/kernel/entry_64.S
> index 3710b8241945..a5afdf0f7fa4 100644
> --- a/arch/x86/kernel/entry_64.S
> +++ b/arch/x86/kernel/entry_64.S
> @@ -804,6 +804,54 @@ retint_swapgs: /*
Hi
On 01/08/2015 06:57 AM, Paolo Bonzini wrote:
>
>
> On 02/01/2015 04:05, Nicholas Krause wrote:
>> Adds the function kvm_vcpu_set_pending_timer for setting a pending timer on
>> a virtual cpu for x86 systems. This
>> function calls kvm_make_request internally as moved over from lapic.c with
This small series fixes a number of issues that Christoffer and I have
been trying to nail down for a while, having to do with the host dying
under load (swapping), and also with the way we deal with caches in
general (and with set/way operation in particular):
- The first patch, courtesy of Steve
Let's assume a guest has created an uncached mapping, and written
to that page. Let's also assume that the host uses a cache-coherent
IO subsystem. Let's finally assume that the host is under memory
pressure and starts to swap things out.
Before this "uncached" page is evicted, we need to make sur
When handling a fault in stage-2, we need to resync I$ and D$, just
to be sure we don't leave any old cache line behind.
That's very good, except that we do so using the *user* address.
Under heavy load (swapping like crazy), we may end up in a situation
where the page gets mapped in stage-2 while
From: Steve Capper
ptep_clear_flush_young_notify and pmdp_clear_flush_young_notify both
call the notifiers *after* the pte/pmd has been made young.
This can cause problems with KVM that relies on being able to block
MMU notifiers when carrying out maintenance of second stage
descriptors.
This p
Trying to emulate the behaviour of set/way cache ops is fairly
pointless, as there are too many ways we can end-up missing stuff.
Also, there is some system caches out there that simply ignore
set/way operations.
So instead of trying to implement them, let's convert it to VA ops,
and use them as a
On 02/01/2015 04:05, Nicholas Krause wrote:
> Adds the function kvm_vcpu_set_pending_timer for setting a pending timer on a
> virtual cpu for x86 systems. This
> function calls kvm_make_request internally as moved over from lapic.c with
> the arugments of the virtual cpu passed
> to the functi
On Wed, Jan 07, 2015 at 07:01:10PM -0800, Mario Smarduch wrote:
> On 01/07/2015 05:05 AM, Christoffer Dall wrote:
> > On Sun, Dec 14, 2014 at 11:28:08PM -0800, Mario Smarduch wrote:
> >> This patch adds the same support for PUD huge page as for PMD. Huge PUD is
> >> write protected for initial mem
On Wed, Jan 07, 2015 at 05:51:15PM -0800, Mario Smarduch wrote:
> On 01/07/2015 04:47 AM, Christoffer Dall wrote:
> > On Sun, Dec 14, 2014 at 11:28:07PM -0800, Mario Smarduch wrote:
> >> This patch enables ARMv8 ditry page logging support. Plugs ARMv8 into
> >> generic
> >
> >
On Wed, Jan 07, 2015 at 05:43:18PM -0800, Mario Smarduch wrote:
> Hi Christoffer,
> before going through your comments, I discovered that
> in 3.18.0-rc2 - a generic __get_user_pages_fast()
> was implemented, now ARM picks this up. This causes
> gfn_to_pfn_prot() to return meaningful 'writable'
>
On 25/12/2014 01:52, Nadav Amit wrote:
> Few more emulator fixes. Each is logically independent from the others.
>
> The first one is the most interesting one. It appears that the current
> behavior may cause the VM to enter the page-fault handler twice on certain
> faulting write accesses. If
These API changes were introduced in 3.19-rc1. Update source pointer
since this is the only required change for 3.19-rc1.
Signed-off-by: Paolo Bonzini
---
external-module-compat-comm.h | 4
linux | 2 +-
2 files changed, 5 insertions(+), 1 deletion(-)
diff --git a/
These are needed for KVM changes in 3.18.
Recent kernels added a separate feature word for XSAVE features, and KVM's
CPUID code is relying on the new definition. Except for cpu_has_xsaves,
it's never accessing the feature itself: wrap cpu_has_xsaves with
kvm_cpu_has_xsaves, and then there is no p
These API changes were introduced in 3.18.
Signed-off-by: Paolo Bonzini
---
external-module-compat-comm.h | 15 +++
1 file changed, 15 insertions(+)
diff --git a/external-module-compat-comm.h b/external-module-compat-comm.h
index 1717ba3..6866658 100644
--- a/external-module-compat-
These API changes were introduced in 3.18. Update source pointer
since 3.18 now compiles.
Signed-off-by: Paolo Bonzini
---
external-module-compat-comm.h | 9 +
linux | 2 +-
2 files changed, 10 insertions(+), 1 deletion(-)
diff --git a/external-module-compat-com
The largest changes are in the XSAVE support. Recent kernels added a
separate feature word for XSAVE features, and KVM's CPUID code is relying
on the new definition. Except for cpu_has_xsaves, it's never accessing
the feature itself: wrap cpu_has_xsaves with kvm_cpu_has_xsaves, and
then there is
On Wed, Jan 07, 2015 at 11:58:00PM +0300, Sergei Shtylyov wrote:
> Hello.
>
> On 01/07/2015 11:55 AM, Michael S. Tsirkin wrote:
>
> >commit 8b38694a2dc8b18374310df50174f1e4376d6824
> > vhost/net: virtio 1.0 byte swap
> >had this chunk:
> >- heads[headcount - 1].len += datalen;
> >+
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