This patch adds support for 2nd stage page fault handling while dirty page
logging. On huge page faults, huge pages are dissolved to normal pages, and
rebuilding of 2nd stage huge pages is blocked. In case migration is
canceled this restriction is removed and huge pages may be rebuilt again.
On 01/09/2015 02:24 AM, Christoffer Dall wrote:
On Thu, Jan 08, 2015 at 08:28:46AM -0800, Mario Smarduch wrote:
On 01/08/2015 02:45 AM, Christoffer Dall wrote:
On Wed, Jan 07, 2015 at 05:43:18PM -0800, Mario Smarduch wrote:
Hi Christoffer,
before going through your comments, I discovered
On Fri, Nov 07, 2014 at 03:58:19PM -0800, Andy Lutomirski wrote:
We used to optimize rescheduling and audit on syscall exit. Now that
the full slow path is reasonably fast, remove these optimizations.
This adds something like 10ns to the previously optimized paths on my
computer, presumably
Currently we reset the KVM interrupt line on initializing the 8250
serial device emulation.
For ARM this creates a problem where we use the in-kernel IRQ chip
before having fully initialized it. But with the new kernel interface
we cannot finish the GIC initialization before we know the number of
On 9 January 2015 at 14:16, Marc Zyngier marc.zyng...@arm.com wrote:
On 09/01/15 13:03, Peter Maydell wrote:
When we reset a cpu by re-calling KVM_ARM_VCPU_INIT, that doesn't
mean we get a new VMID for it, though, does it? I thought that
what causes the icache flush to happen for the reset
On 09/01/2015 16:12, Radim Krčmář wrote:
The chipset doesn't support it. :(
I meant that we need to recompute PI entries for lowest priority
interrupts every time guest's TPR changes.
Luckily, Linux doesn't use TPR, but other OS might be a reason to drop
lowest priority from PI
On 09/01/2015 09:44, Kai Huang wrote:
When software changes D bit (either from 1 to 0, or 0 to 1), the corresponding
TLB entity in the hardware won't be updated immediately. We should flush it to
guarantee the consistence of D bit between TLB and MMU page table in memory.
This is required if
On Thu, Jan 08, 2015 at 08:28:46AM -0800, Mario Smarduch wrote:
On 01/08/2015 02:45 AM, Christoffer Dall wrote:
On Wed, Jan 07, 2015 at 05:43:18PM -0800, Mario Smarduch wrote:
Hi Christoffer,
before going through your comments, I discovered that
in 3.18.0-rc2 - a generic
On Thu, Jan 08, 2015 at 08:41:15AM -0800, Mario Smarduch wrote:
[...]
I'm just thinking here, why do we need to check if we get a valid pud
back here, but we don't need the equivalent check in dissolve_pmd from
patch 7?
kvm_pud_huge() doesn't check bit 0 for invalid entry, but
On 01/09/2015 04:44 PM, Kai Huang wrote:
When software changes D bit (either from 1 to 0, or 0 to 1), the corresponding
TLB entity in the hardware won't be updated immediately. We should flush it to
guarantee the consistence of D bit between TLB and MMU page table in memory.
This is required
When software changes D bit (either from 1 to 0, or 0 to 1), the corresponding
TLB entity in the hardware won't be updated immediately. We should flush it to
guarantee the consistence of D bit between TLB and MMU page table in memory.
This is required if some specific hardware feature uses D-bit
On 09/01/2015 09:44, Kai Huang wrote:
When software changes D bit (either from 1 to 0, or 0 to 1), the corresponding
TLB entity in the hardware won't be updated immediately. We should flush it to
guarantee the consistence of D bit between TLB and MMU page table in memory.
This is required if
On 09/01/15 15:28, Peter Maydell wrote:
On 9 January 2015 at 14:16, Marc Zyngier marc.zyng...@arm.com wrote:
On 09/01/15 13:03, Peter Maydell wrote:
When we reset a cpu by re-calling KVM_ARM_VCPU_INIT, that doesn't
mean we get a new VMID for it, though, does it? I thought that
what causes the
2015-01-09 15:56+0100, Paolo Bonzini:
On 09/01/2015 15:54, Radim Krčmář wrote:
There are two points relevant to this patch in new KVM's implementation,
(KVM: x86: amend APIC lowest priority arbitration,
https://lkml.org/lkml/2015/1/9/362)
1) lowest priority depends on TPR
2)
2015-01-09 16:18+0100, Paolo Bonzini:
On 09/01/2015 16:12, Radim Krčmář wrote:
The chipset doesn't support it. :(
I meant that we need to recompute PI entries for lowest priority
interrupts every time guest's TPR changes.
Luckily, Linux doesn't use TPR, but other OS might be a
On Fri, Jan 9, 2015 at 7:53 AM, Borislav Petkov b...@alien8.de wrote:
On Fri, Nov 07, 2014 at 03:58:19PM -0800, Andy Lutomirski wrote:
We used to optimize rescheduling and audit on syscall exit. Now that
the full slow path is reasonably fast, remove these optimizations.
This adds something
Indeed, any invalid memslots should be new-npages = 0,
new-base_gfn = 0 and new-flags = 0 at the same time.
Signed-off-by: Tiejun Chen tiejun.c...@intel.com
---
Paolo,
This is just a small cleanup to follow-up commit, efbeec7098ee, fix
sorting of memslots with base_gfn == 0.
Tiejun
On 09/01/15 11:19, Christoffer Dall wrote:
On Thu, Jan 08, 2015 at 11:59:07AM +, Marc Zyngier wrote:
Trying to emulate the behaviour of set/way cache ops is fairly
pointless, as there are too many ways we can end-up missing stuff.
Also, there is some system caches out there that simply
On Fri, Jan 09, 2015 at 11:38:19AM +, Marc Zyngier wrote:
[...]
@@ -258,12 +272,24 @@ bool access_sctlr(struct kvm_vcpu *vcpu,
const struct coproc_params *p,
const struct coproc_reg *r)
{
+ bool was_enabled = vcpu_has_cache_enabled(vcpu);
+
On Thu, Jan 08, 2015 at 11:59:08AM +, Marc Zyngier wrote:
Let's assume a guest has created an uncached mapping, and written
to that page. Let's also assume that the host uses a cache-coherent
IO subsystem. Let's finally assume that the host is under memory
pressure and starts to swap
On 09/01/15 13:03, Peter Maydell wrote:
On 9 January 2015 at 12:50, Christoffer Dall
christoffer.d...@linaro.org wrote:
On Thu, Jan 08, 2015 at 03:21:50PM +, Peter Maydell wrote:
If this is the first instruction in the guest (ie we've just
(warm) reset the VM and are running the kernel as
On 09/01/15 12:30, Christoffer Dall wrote:
On Thu, Jan 08, 2015 at 11:59:08AM +, Marc Zyngier wrote:
Let's assume a guest has created an uncached mapping, and written
to that page. Let's also assume that the host uses a cache-coherent
IO subsystem. Let's finally assume that the host is
Lowest priority should take the task priority into account.
SDM 10.6.2.4 Lowest Priority Delivery Mode.
(Too long to quote; second and last paragraphs are relevant.)
Before this patch, we strived to have the same amount of handled
lowest-priority interrupts on all VCPUs.
This is only a
-Original Message-
From: j...@8bytes.org [mailto:j...@8bytes.org]
Sent: Friday, January 09, 2015 8:46 PM
To: Wu, Feng
Cc: t...@linutronix.de; mi...@redhat.com; h...@zytor.com; x...@kernel.org;
g...@kernel.org; pbonz...@redhat.com; dw...@infradead.org;
alex.william...@redhat.com;
On Thu, Jan 08, 2015 at 11:59:09AM +, Marc Zyngier wrote:
When handling a fault in stage-2, we need to resync I$ and D$, just
to be sure we don't leave any old cache line behind.
That's very good, except that we do so using the *user* address.
Under heavy load (swapping like crazy), we
Hi,
I'm trying to add a new virtio device.
I've managed to make qemu connect my virtio device to the pci bus.
I'm now trying to make a dummy driver in the guest's kernel.
My lspci binary version isn't very verbose. For example the output for
lspci and lspci -n are the same:
00:00.0 Class 0604:
Hi Feng,
On Tue, Jan 06, 2015 at 01:10:19AM +, Wu, Feng wrote:
Ping...
Hi Joerg David,
Could you please have a look at the IOMMU part of this series (patch 02 - 04,
patch 06 - 09 , patch 26)?
Hi Thomas, Ingo, Peter,
Could you please have a look at this series, especially for
On Thu, Jan 08, 2015 at 03:21:50PM +, Peter Maydell wrote:
On 8 January 2015 at 15:06, Marc Zyngier marc.zyng...@arm.com wrote:
On 08/01/15 13:16, Peter Maydell wrote:
ASID cached VIVT icaches are also VMID tagged. It is thus impossible for
stale cache lines to come with a new page. And
On 9 January 2015 at 12:50, Christoffer Dall
christoffer.d...@linaro.org wrote:
On Thu, Jan 08, 2015 at 03:21:50PM +, Peter Maydell wrote:
If this is the first instruction in the guest (ie we've just
(warm) reset the VM and are running the kernel as loaded into the guest
by QEMU/kvmtool)
On Fri, Nov 07, 2014 at 03:58:18PM -0800, Andy Lutomirski wrote:
+ /*
+ * Try to use SYSRET instead of IRET if we're returning to
+ * a completely clean 64-bit userspace context.
+ */
+ movq (RCX-R11)(%rsp), %rcx
+ cmpq %rcx,(RIP-R11)(%rsp) /* RCX ==
On Thu, Jan 08, 2015 at 11:59:07AM +, Marc Zyngier wrote:
Trying to emulate the behaviour of set/way cache ops is fairly
pointless, as there are too many ways we can end-up missing stuff.
Also, there is some system caches out there that simply ignore
set/way operations.
So instead of
2014-12-12 23:14+0800, Feng Wu:
This patch defines a new interface kvm_find_dest_vcpu for
VT-d PI, which can returns the destination vCPU of the
interrupt for guests.
Since VT-d PI cannot handle broadcast/multicast interrupt,
Here we only handle Fixed and Lowest priority interrupts.
The
On 09/01/2015 15:54, Radim Krčmář wrote:
There are two points relevant to this patch in new KVM's implementation,
(KVM: x86: amend APIC lowest priority arbitration,
https://lkml.org/lkml/2015/1/9/362)
1) lowest priority depends on TPR
2) there is no need for balancing
(1) has to be
33 matches
Mail list logo
