On Fri, Apr 17, 2015 at 12:16:18PM +0200, Paolo Bonzini wrote:
>
>
>On 17/04/2015 07:10, Wanpeng Li wrote:
>>> >
>>> >Before the change, if guest CR4.MCE==0, then the machine check is
>>> >escalated to Catastrophic Error (CATERR) and the machine dies.
>> Could you point out which section of SDM des
If the host sets hardware breakpoints to debug the guest, and a task-switch
occurs in the guest, the architectural DR7 will not be updated. The effective
DR7 would be updated instead.
This fix puts the DR7 update during task-switch emulation, so it now uses the
standard DR setting mechanism instea
On 19/04/2015 18:50, Brad Campbell wrote:
> And I can confidently state that over the years I've seen this happen a
> number of times, but in each case I was using qemu with an SDL console
> as a user-interactive VM, and a moving the mouse would restore network
> connectivity. It was obviously se
Paolo Bonzini wrote:
>
>
> On 19/04/2015 14:18, Nadav Amit wrote:
>> If the host sets hardware breakpoints to debug the guest, and a task-switch
>> occurs in the guest, the architectural DR7 will not be updated. The effective
>> DR7 would be updated instead.
>>
>> This fix uses the standard DR
On 19/04/2015 15:16, Nadav Amit wrote:
> Hi,
>
> I would appreciate if someone briefly explains the design choice that leaded
> to separating the x86 emulator from the rest of x86 code, i.e., making it
> oblivious to VCPUs and using the x86_emulate_ops as an interface.
I think the reason was to
On 19/04/2015 14:18, Nadav Amit wrote:
> If the host sets hardware breakpoints to debug the guest, and a task-switch
> occurs in the guest, the architectural DR7 will not be updated. The effective
> DR7 would be updated instead.
>
> This fix uses the standard DR setting mechanism instead of the
On 19/04/15 23:48, Nadav Amit wrote:
Brad Campbell wrote:
On 13/04/15 22:02, Paolo Bonzini wrote:
On 13/04/2015 14:45, Brad Campbell wrote:
G'day Paolo,
Yes, on AMD and I've tried hard to reproduce it on Intel and been unable
to thus far.
Now you mention it may be AMD specific, I have a s
Brad Campbell wrote:
>
> On 13/04/15 22:02, Paolo Bonzini wrote:
>> On 13/04/2015 14:45, Brad Campbell wrote:
>>> G'day Paolo,
>>>
>>> Yes, on AMD and I've tried hard to reproduce it on Intel and been unable
>>> to thus far.
>>>
>>> Now you mention it may be AMD specific, I have a spare mother
On 13/04/15 22:02, Paolo Bonzini wrote:
On 13/04/2015 14:45, Brad Campbell wrote:
G'day Paolo,
Yes, on AMD and I've tried hard to reproduce it on Intel and been unable
to thus far.
Now you mention it may be AMD specific, I have a spare motherboard and
processor sitting in a drawer. I'll bolt
Hi,
I would appreciate if someone briefly explains the design choice that leaded
to separating the x86 emulator from the rest of x86 code, i.e., making it
oblivious to VCPUs and using the x86_emulate_ops as an interface.
Thanks,
Nadav
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If the host sets hardware breakpoints to debug the guest, and a task-switch
occurs in the guest, the architectural DR7 will not be updated. The effective
DR7 would be updated instead.
This fix uses the standard DR setting mechanism instead of the one that was
previously used. As a bonus, the updat
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