On 10/29/2013 07:47 AM, Alex Williamson wrote:
On Mon, 2013-10-28 at 21:29 -0400, Don Dutile wrote:
On 09/30/2013 11:37 AM, Bhushan Bharat-R65777 wrote:
-Original Message-
From: iommu-boun...@lists.linux-foundation.org [mailto:iommu-
boun...@lists.linux-foundation.org] On Behalf Of
On 09/30/2013 11:37 AM, Bhushan Bharat-R65777 wrote:
-Original Message-
From: iommu-boun...@lists.linux-foundation.org [mailto:iommu-
boun...@lists.linux-foundation.org] On Behalf Of Antonios Motakis
Sent: Monday, September 30, 2013 8:59 PM
To: kvm...@lists.cs.columbia.edu; alex.willia
On 10/02/2013 08:14 AM, Alexander Graf wrote:
On 01.10.2013, at 21:21, Yoder Stuart-B08248 wrote:
static int __init vfio_iommu_type1_init(void)
{
- if (!iommu_present(&pci_bus_type))
+#ifdef CONFIG_PCI
+ if (iommu_present(&pci_bus_type)) {
+ iommu_bus_type =&pci_bus_t
On 06/26/2013 03:03 PM, Alex Williamson wrote:
On Mon, 2013-06-24 at 11:43 -0600, Bjorn Helgaas wrote:
On Wed, Jun 19, 2013 at 6:43 AM, Don Dutile wrote:
On 06/18/2013 10:52 PM, Bjorn Helgaas wrote:
On Tue, Jun 18, 2013 at 5:03 PM, Don Dutile wrote:
On 06/18/2013 06:22 PM, Alex
On 06/18/2013 10:52 PM, Bjorn Helgaas wrote:
On Tue, Jun 18, 2013 at 5:03 PM, Don Dutile wrote:
On 06/18/2013 06:22 PM, Alex Williamson wrote:
On Tue, 2013-06-18 at 15:31 -0600, Bjorn Helgaas wrote:
On Tue, Jun 18, 2013 at 12:20 PM, Alex Williamson
wrote:
On Tue, 2013-06-18 at 11:28
On 06/18/2013 06:22 PM, Alex Williamson wrote:
On Tue, 2013-06-18 at 15:31 -0600, Bjorn Helgaas wrote:
On Tue, Jun 18, 2013 at 12:20 PM, Alex Williamson
wrote:
On Tue, 2013-06-18 at 11:28 -0600, Bjorn Helgaas wrote:
On Thu, May 30, 2013 at 12:40:19PM -0600, Alex Williamson wrote:
PCIe ACS (
On 05/30/2013 02:40 PM, Alex Williamson wrote:
PCIe ACS (Access Control Services) is the PCIe 2.0+ feature that
allows us to control whether transactions are allowed to be redirected
in various subnodes of a PCIe topology. For instance, if two
endpoints are below a root port or downsteam switch
On 02/28/2013 10:24 AM, Michael S. Tsirkin wrote:
OK we talked about this a while ago, here's
a summary and some proposals:
At the moment, virtio PCI uses IO BARs for all accesses.
The reason for IO use is the cost of different VM exit types
of transactions and their emulation on KVM on x86
(it
On 12/15/2012 05:16 PM, Robert Hancock wrote:
On 12/14/2012 03:32 PM, Don Dutile wrote:
On 12/13/2012 04:50 AM, Jason Gao wrote:
Dear List:
Description of problem:
After installed Centos 6.3(RHEL6.3) on my Dell R710(lastest
bios:Version: 6.3.0,Release Date: 07/24/2012) server,and updated
On 12/13/2012 09:01 PM, Jason Gao wrote:
On Fri, Dec 14, 2012 at 12:23 AM, Alex Williamson
wrote:
Device 03:00.0 is your raid controller:
03:00.0 RAID bus controller: LSI Logic / Symbios Logic MegaRAID SAS 1078 (rev
04)
For some reason it's trying to read from ffe65000, ffe8a000, ffe89000,
On 12/13/2012 09:01 PM, Jason Gao wrote:
On Fri, Dec 14, 2012 at 12:23 AM, Alex Williamson
wrote:
Device 03:00.0 is your raid controller:
03:00.0 RAID bus controller: LSI Logic / Symbios Logic MegaRAID SAS 1078 (rev
04)
For some reason it's trying to read from ffe65000, ffe8a000, ffe89000,
On 12/13/2012 04:50 AM, Jason Gao wrote:
Dear List:
Description of problem:
After installed Centos 6.3(RHEL6.3) on my Dell R710(lastest
bios:Version: 6.3.0,Release Date: 07/24/2012) server,and updated
lastest kernel "2.6.32-279.14.1.el6.x86_64",I want to use the Intel
82576 ET Dual Port nic's SR
On 11/13/2012 11:04 AM, Li, Sibai wrote:
-Original Message-
From: Jason Gao [mailto:pkill.2...@gmail.com]
Sent: Tuesday, November 13, 2012 5:38 AM
To: bhelg...@google.com; Rose, Gregory V; Li, Sibai
Cc: ddut...@redhat.com; Kirsher, Jeffrey T; linux-kernel; netdev; kvm; e1000-
de...@lis
On 11/09/2012 10:26 AM, Bjorn Helgaas wrote:
[+ linux-pci, Yinghai]
On Thu, Nov 8, 2012 at 8:59 PM, Jason Gao wrote:
The BIOS in your machine doesn't support SR-IOV. You'll need to ask the
manufacturer for a BIOS upgrade, if in fact one is available. Sometimes
they're not.
very thanks Gr
On 06/08/2012 02:02 PM, Myron Stowe wrote:
On Fri, Jun 8, 2012 at 11:31 AM, Bjorn Helgaas wrote:
On Fri, Jun 8, 2012 at 1:01 AM, Xudong Hao wrote:
The series of patches enable LTR and OBFF before device is used by driver, and
introduce a couple of functions to save/restore LTR latency value.
While you are making the other recommended fixes, could
you add/create a pci_obff_supported() function, like the pci_ltr_supported()
function, and more importantly, add it to the pci_disable_obff() function?
The latter does not check that DEVCAP2 is supported, and thus, could be
writing to non-exi
On 05/24/2012 06:46 PM, Alex Williamson wrote:
On Thu, 2012-05-24 at 17:38 -0400, Don Dutile wrote:
On 05/22/2012 01:05 AM, Alex Williamson wrote:
x86 is probably the wrong name for this VFIO IOMMU driver, but x86
is the primary target for it. This driver support a very simple
usage model
On 05/22/2012 01:04 AM, Alex Williamson wrote:
Version 2 incorporating acks and feedback from v1. The PCI DMA quirk
and ACS check are reworked, sysfs iommu groups ABI Documentation
added as well as numerous other fixes, including patches from Alexey
Kardashevskiy towards supporting POWER usage o
On 05/22/2012 01:05 AM, Alex Williamson wrote:
Fill in many missing definitions and add sizeof fields for many
sections allowing for more extensive config parsing.
Signed-off-by: Alex Williamson
---
overall, i'm very glad to see defines instead of hardcoded numbers in the code,
but
in
On 05/22/2012 01:05 AM, Alex Williamson wrote:
x86 is probably the wrong name for this VFIO IOMMU driver, but x86
is the primary target for it. This driver support a very simple
usage model using the existing IOMMU API. The IOMMU is expected to
support the full host address space with no specia
On 05/22/2012 01:05 AM, Alex Williamson wrote:
In a PCI environment, transactions aren't always required to reach
the root bus before being re-routed. Intermediate switches between
an endpoint and the root bus can redirect DMA back downstream before
things like IOMMUs have a chance to intervene.
On 05/22/2012 01:04 AM, Alex Williamson wrote:
Add back group support for AMD& Intel. amd_iommu already tracks
devices and has init and uninit routines to manage groups.
intel-iommu does this on the fly, so we make use of the notifier
support built into iommu groups to create and remove groups.
On 05/21/2012 10:59 AM, Alex Williamson wrote:
On Mon, 2012-05-21 at 09:31 -0400, Don Dutile wrote:
On 05/18/2012 10:47 PM, Alex Williamson wrote:
On Fri, 2012-05-18 at 19:00 -0400, Don Dutile wrote:
On 05/18/2012 06:02 PM, Alex Williamson wrote:
On Wed, 2012-05-16 at 09:29 -0400, Don Dutile
On 05/18/2012 10:47 PM, Alex Williamson wrote:
On Fri, 2012-05-18 at 19:00 -0400, Don Dutile wrote:
On 05/18/2012 06:02 PM, Alex Williamson wrote:
On Wed, 2012-05-16 at 09:29 -0400, Don Dutile wrote:
On 05/15/2012 05:09 PM, Alex Williamson wrote:
On Tue, 2012-05-15 at 13:56 -0600, Bjorn
On 05/18/2012 06:02 PM, Alex Williamson wrote:
On Wed, 2012-05-16 at 09:29 -0400, Don Dutile wrote:
On 05/15/2012 05:09 PM, Alex Williamson wrote:
On Tue, 2012-05-15 at 13:56 -0600, Bjorn Helgaas wrote:
On Mon, May 14, 2012 at 4:49 PM, Alex Williamson
wrote:
On Mon, 2012-05-14 at 16:02
On 05/15/2012 05:09 PM, Alex Williamson wrote:
On Tue, 2012-05-15 at 13:56 -0600, Bjorn Helgaas wrote:
On Mon, May 14, 2012 at 4:49 PM, Alex Williamson
wrote:
On Mon, 2012-05-14 at 16:02 -0600, Bjorn Helgaas wrote:
On Fri, May 11, 2012 at 4:56 PM, Alex Williamson
wrote:
In a PCIe environm
On 12/13/2011 03:40 AM, Andreas Hartmann wrote:
Hello Don!
Andreas,
sorry for the delay, I don't follow this email list frequently (read: !daily).
Am Tue, 13 Dec 2011 01:21:41 +0100
schrieb Andreas Hartmann:
Am Mon, 12 Dec 2011 13:36:36 -0500
schrieb Don Dutile:
On 12/12/2011 06:
On 12/12/2011 06:15 AM, Andreas Hartmann wrote:
Hello!
I've got a few questions to a problem, which already was analyzed here
sometime ago:
http://markmail.org/message/dspovwvzp3wtdrf6#query:+page:1+mid:i2oph4xwfmiknt3y+state:results
My situation is a bit different. I do have two PCI cards (a L
On 10/02/2011 05:56 AM, Michael S. Tsirkin wrote:
On Wed, Sep 28, 2011 at 08:20:33PM -0400, Donald Dutile wrote:
commit f9c29774d2174df6ffc20becec20928948198914
changed the PCIe Capability structure version check
from if> 2 fail, to if ==1, size=x, if ==2, size=y,
else fail.
Turns out the 82599
On 09/07/2011 03:44 PM, Greg KH wrote:
On Wed, Sep 07, 2011 at 09:19:19PM +0200, Joerg Roedel wrote:
Hi Greg,
the bus_set_iommu() function will be called by the IOMMU driver. There
can be different drivers for the same bus, depending on the hardware. On
PCI for example, there can be the Intel o
On 08/25/2011 06:54 AM, Roedel, Joerg wrote:
Hi Alex,
On Wed, Aug 24, 2011 at 05:13:49PM -0400, Alex Williamson wrote:
Is this roughly what you're thinking of for the iommu_group component?
Adding a dev_to_group iommu ops callback let's us consolidate the sysfs
support in the iommu base. Would
On 07/25/2011 04:20 PM, Alex Williamson wrote:
On Mon, 2011-07-25 at 15:37 -0400, Don Dutile wrote:
On 07/24/2011 06:58 AM, Michael S. Tsirkin wrote:
On Sun, Jul 24, 2011 at 11:41:10AM +0300, Michael S. Tsirkin wrote:
On Sun, Jul 24, 2011 at 11:12:44AM +0300, Michael S. Tsirkin wrote:
On Fri
On 07/24/2011 06:58 AM, Michael S. Tsirkin wrote:
On Sun, Jul 24, 2011 at 11:41:10AM +0300, Michael S. Tsirkin wrote:
On Sun, Jul 24, 2011 at 11:12:44AM +0300, Michael S. Tsirkin wrote:
On Fri, Jul 22, 2011 at 02:35:47PM -0700, Chris Wright wrote:
* Alex Williamson (alex.william...@redhat.com)
On 07/21/2011 01:02 PM, Alex Williamson wrote:
On Thu, 2011-07-21 at 12:39 -0400, Donald Dutile wrote:
v2: do local boundary check with respect to legacy PCI header length,
and don't depend on it in pci_add_capability().
: fix compilation, and change else>2 to simple else for all other c
On 07/21/2011 04:11 AM, Michael S. Tsirkin wrote:
On Wed, Jul 20, 2011 at 07:49:34PM -0400, Donald Dutile wrote:
Bounds check to avoid walking off config_map[]
and corrupting what is after it.
Signed-off-by: Donald Dutile
cc: Alex Williamson
cc: Michael S. Tsirkin
---
hw/pci.c | 16 +++
On 07/20/2011 10:43 PM, Alex Williamson wrote:
On Wed, 2011-07-20 at 19:51 -0400, Donald Dutile wrote:
Corrected default size of PCIe Cap Structure from 0x3c to 0x34.
0x34 is min size for version 2 Cap Structure for an endpoint.
0x3c value failed on a real device that aligned this
structure at
Avi Kivity wrote:
On 11/09/2010 03:44 PM, Jan Kiszka wrote:
>
> Oh yes, I read the code but it didn't register. Of course this change
> is quite necessary.
>
> (I understood you to mean that the PCI 2.3 reset doesn't reset
> everything, but that isn't what you said).
What the hardware make
Alex Williamson wrote:
> Commit 909bfdba fixed a hole with not closing resource file descriptors
> but we need to be more careful about tracking which are real fds,
> otherwise we might close fd 0, which doesn't work out so well for stdio.
>
> Signed-off-by: Alex Williamson
> ---
>
> v2: fix qe
Alex Williamson wrote:
Commit 909bfdba fixed a hole with not closing resource file descriptors
but we need to be more careful about tracking which are real fds,
otherwise we might close fd 0, which doesn't work out so well for stdio.
Signed-off-by: Alex Williamson
---
hw/device-assignment.c |
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