Re: [PATCH v8 09/20] KVM: ARM64: Add access handler for event counter register

On 22/12/15 08:08, Shannon Zhao wrote: > From: Shannon Zhao > > These kind of registers include PMEVCNTRn, PMCCNTR and PMXEVCNTR which > is mapped to PMEVCNTRn. > > The access handler translates all aarch32 register offsets to aarch64 > ones and uses vcpu_sys_reg() to

[PATCH] arm64: KVM: Fix AArch64 guest userspace exception injection

fixes it by implementing section D1.10.2 of the ARMv8 ARM, and in particular table D1-7 ("Vector offsets from vector table base address"), which describes which vector to use depending on the source exception level and type (synchronous, IRQ, FIQ or SError). Signed-off-by: Marc Zyngier

Re: [PATCH v8 04/20] KVM: ARM64: Add access handler for PMCR register

On 22/12/15 08:07, Shannon Zhao wrote: > From: Shannon Zhao > > Add reset handler which gets host value of PMCR_EL0 and make writable > bits architecturally UNKNOWN except PMCR.E which is zero. Add an access > handler for PMCR. > > Signed-off-by: Shannon Zhao

Re: [PATCH v8 11/20] KVM: ARM64: Add access handler for PMINTENSET and PMINTENCLR register

On 22/12/15 08:08, Shannon Zhao wrote: > From: Shannon Zhao > > Since the reset value of PMINTENSET and PMINTENCLR is UNKNOWN, use > reset_unknown for its reset handler. Add a handler to emulate writing > PMINTENSET or PMINTENCLR register. > > Signed-off-by: Shannon

Re: [PATCH v8 01/20] ARM64: Move PMU register related defines to asm/pmu.h

g> > Signed-off-by: Shannon Zhao <shannon.z...@linaro.org> Acked-by: Marc Zyngier <marc.zyng...@arm.com> M. -- Jazz is not dead. It just smells funny... -- To unsubscribe from this list: send the line "unsubscribe kvm" in the body of a message to

Re: [PATCH v8 06/20] KVM: ARM64: Add access handler for PMCEID0 and PMCEID1 register

On 22/12/15 08:08, Shannon Zhao wrote: > From: Shannon Zhao > > Add access handler which gets host value of PMCEID0 or PMCEID1 when > guest access these registers. Writing action to PMCEID0 or PMCEID1 is > UNDEFINED. > > Signed-off-by: Shannon Zhao

Re: [PATCH v8 05/20] KVM: ARM64: Add access handler for PMSELR register

On 22/12/15 08:08, Shannon Zhao wrote: > From: Shannon Zhao > > Since the reset value of PMSELR_EL0 is UNKNOWN, use reset_unknown for > its reset handler. When reading PMSELR, return the PMSELR.SEL field to > guest. > > Signed-off-by: Shannon Zhao

Re: [PATCH v8 13/20] KVM: ARM64: Add access handler for PMSWINC register

On 22/12/15 08:08, Shannon Zhao wrote: > From: Shannon Zhao > > Add access handler which emulates writing and reading PMSWINC > register and add support for creating software increment event. > > Signed-off-by: Shannon Zhao > --- >

Re: [PATCH v8 16/20] KVM: ARM64: Add access handler for PMUSERENR register

On 22/12/15 08:08, Shannon Zhao wrote: > From: Shannon Zhao > > This register resets as unknown in 64bit mode while it resets as zero > in 32bit mode. Here we choose to reset it as zero for consistency. > > PMUSERENR_EL0 holds some bits which decide whether PMU

Re: [PATCH v8 03/20] KVM: ARM64: Add offset defines for PMU registers

ao <shannon.z...@linaro.org> Reviewed-by: Marc Zyngier <marc.zyng...@arm.com> M. -- Jazz is not dead. It just smells funny... -- To unsubscribe from this list: send the line "unsubscribe kvm" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html

Re: [PATCH v8 08/20] KVM: ARM64: Add access handler for event typer register

On 07/01/16 12:09, Shannon Zhao wrote: > > > On 2015/12/22 16:08, Shannon Zhao wrote: >> From: Shannon Zhao >> >> These kind of registers include PMEVTYPERn, PMCCFILTR and PMXEVTYPER >> which is mapped to PMEVTYPERn or PMCCFILTR. >> >> The access handler translates all

Re: [PATCH v8 19/20] KVM: ARM64: Free perf event of PMU when destroying vcpu

On Tue, 22 Dec 2015 16:08:14 +0800 Shannon Zhao <zhaoshengl...@huawei.com> wrote: > From: Shannon Zhao <shannon.z...@linaro.org> > > When KVM frees VCPU, it needs to free the perf_event of PMU. > > Signed-off-by: Shannon Zhao <shannon.z...@linaro.org> Rev

Re: [PATCH v8 07/20] KVM: ARM64: PMU: Add perf event map and introduce perf event creating function

On Tue, 22 Dec 2015 16:08:02 +0800 Shannon Zhao wrote: > From: Shannon Zhao > > When we use tools like perf on host, perf passes the event type and the > id of this event type category to kernel, then kernel will map them to > hardware event

Re: [PATCH v8 00/20] KVM: ARM64: Add guest PMU support

On 07/01/16 14:12, Will Deacon wrote: > On Thu, Jan 07, 2016 at 02:10:38PM +0000, Marc Zyngier wrote: >> On 22/12/15 08:07, Shannon Zhao wrote: >>> From: Shannon Zhao <shannon.z...@linaro.org> >>> >>> This patchset adds guest PMU support for KVM on ARM

[PATCH 18/31] arm64: KVM: Add panic handling

Add the panic handler, together with the small bits of assembly code to call the kernel's panic implementation. Signed-off-by: Marc Zyngier <marc.zyng...@arm.com> Reviewed-by: Christoffer Dall <christoffer.d...@linaro.org> --- arch/arm64/kvm/hyp/hyp-entry.S | 11 ++- arch/a

[PATCH 17/31] arm64: KVM: HYP mode entry points

Add the entry points for HYP mode (both for hypercalls and exception handling). Signed-off-by: Marc Zyngier <marc.zyng...@arm.com> Reviewed-by: Christoffer Dall <christoffer.d...@linaro.org> --- arch/arm64/kvm/hyp/Makefile| 1 + arch/arm64/kvm/hyp/hyp-e

[PATCH 25/31] ARM: KVM: Cleanup exception injection

the architecture spec. The spurious variables are removed in the process. Reported-by: David Binderman <dcb...@hotmail.com> Reviewed-by: Christoffer Dall <christoffer.d...@linaro.org> Signed-off-by: Marc Zyngier <marc.zyng...@arm.com> --- arch/arm/

[PATCH 22/31] arm64: KVM: Turn system register numbers to an enum

things up a bit. Signed-off-by: Marc Zyngier <marc.zyng...@arm.com> Acked-by: Christoffer Dall <christoffer.d...@linaro.org> --- arch/arm64/include/asm/kvm_asm.h | 76 - arch/arm64/include/asm/kvm_emulate.h | 1 - arch/arm64/include/asm/kvm_ho

[PATCH 21/31] arm64: KVM: Move away from the assembly version of the world switch

This is it. We remove all of the code that has now been rewritten. Signed-off-by: Marc Zyngier <marc.zyng...@arm.com> Acked-by: Christoffer Dall <christoffer.d...@linaro.org> --- arch/arm64/kvm/Makefile |2 - arch/arm64/kvm/hyp.S

[PATCH 09/31] arm64: KVM: Implement system register save/restore

Implement the system register save/restore as a direct translation of the assembly code version. Signed-off-by: Marc Zyngier <marc.zyng...@arm.com> Reviewed-by: Christoffer Dall <christoffer.d...@linaro.org> --- arch/arm64/kvm/hyp/Makefile| 1 + arch/arm64/kvm/hyp/hyp.h |

[PATCH 07/31] arm64: KVM: Implement vgic-v3 save/restore

Implement the vgic-v3 save restore as a direct translation of the assembly code version. Signed-off-by: Marc Zyngier <marc.zyng...@arm.com> --- arch/arm64/kvm/hyp/Makefile | 1 + arch/arm64/kvm/hyp/hyp.h| 3 + arch/arm64/kvm/hyp/vgic-v3-sr.c

[PATCH 19/31] arm64: KVM: Add compatibility aliases

implementation to be overriden by the old one, and everything still work. At a later point, we'll be able to simply drop the old code, and everything will hopefully keep working, thanks to the aliases we have just added. This also saves us repainting all the callers. Signed-off-by: Marc Zyngier

[PATCH 13/31] arm64: KVM: Add patchable function selector

at outputs a brief sequence of code that in turn can be patched, allowing an alternative function to be selected. Signed-off-by: Marc Zyngier <marc.zyng...@arm.com> --- arch/arm64/kvm/hyp/hyp.h | 24 1 file changed, 24 insertions(+) diff --git a/arch/arm64/kvm/hyp/hy

[PATCH 15/31] arm64: KVM: Implement fpsimd save/restore

Implement the fpsimd save restore, keeping the lazy part in assembler (as returning to C would be overkill). Signed-off-by: Marc Zyngier <marc.zyng...@arm.com> Reviewed-by: Christoffer Dall <christoffer.d...@linaro.org> --- arch/arm64/kvm/hyp/Makefile| 1 + arch/arm64/kvm

[PATCH 12/31] arm64: KVM: Implement guest entry

Contrary to the previous patch, the guest entry is fairly different from its assembly counterpart, mostly because it is only concerned with saving/restoring the GP registers, and nothing else. Reviewed-by: Christoffer Dall <christoffer.d...@linaro.org> Signed-off-by: Marc Zyngier <

[PATCH 10/31] arm64: KVM: Implement 32bit system register save/restore

Implement the 32bit system register save/restore as a direct translation of the assembly code version. Signed-off-by: Marc Zyngier <marc.zyng...@arm.com> Reviewed-by: Christoffer Dall <christoffer.d...@linaro.org> --- arch/arm64/kvm/hyp/hyp.h | 2 ++ arch/arm64/kvm/hyp/sysr

[PATCH 02/31] KVM: arm/arm64: Count guest exit due to various reasons

From: Amit Tomar It would add guest exit statistics to debugfs, this can be helpful while measuring KVM performance. [ Renamed some of the field names - Christoffer ] Signed-off-by: Amit Singh Tomar Signed-off-by: Christoffer Dall

[PATCH 03/31] arm64: Add macros to read/write system registers

mari...@arm.com> Cc: Suzuki Poulose <suzuki.poul...@arm.com> Cc: Will Deacon <will.dea...@arm.com> Signed-off-by: Marc Zyngier <marc.zyng...@arm.com> --- arch/arm64/include/asm/sysreg.h | 21 + 1 file changed, 21 insertions(+) diff --git a/arch/arm64/inclu

[PATCH 05/31] arm64: KVM: Implement vgic-v2 save/restore

Implement the vgic-v2 save restore (mostly) as a direct translation of the assembly code version. Signed-off-by: Marc Zyngier <marc.zyng...@arm.com> --- arch/arm64/kvm/Makefile | 1 + arch/arm64/kvm/hyp/Makefile | 5 +++ arch/arm64/kvm/hyp/hyp.h| 3 ++ arch/arm64/k

[PATCH 04/31] arm64: KVM: Add a HYP-specific header file

In order to expose the various EL2 services that are private to the hypervisor, add a new hyp.h file. So far, it only contains mundane things such as section annotation and VA manipulation. Signed-off-by: Marc Zyngier <marc.zyng...@arm.com> --- arch/arm64/kvm/hyp/hyp.

[PATCH 14/31] arm64: KVM: Implement the core world switch

Implement the core of the world switch in C. Not everything is there yet, and there is nothing to re-enter the world switch either. But this already outlines the code structure well enough. Signed-off-by: Marc Zyngier <marc.zyng...@arm.com> Reviewed-by: Christoffer Dall <chri

[PATCH 16/31] arm64: KVM: Implement TLB handling

Implement the TLB handling as a direct translation of the assembly code version. Signed-off-by: Marc Zyngier <marc.zyng...@arm.com> Reviewed-by: Christoffer Dall <christoffer.d...@linaro.org> --- arch/arm64/kvm/hyp/Makefile | 1 + arch/arm64/kvm/hyp/entry.S | 1 + arch/arm64/k

[PATCH 11/31] arm64: KVM: Implement debug save/restore

Implement the debug save restore as a direct translation of the assembly code version. Signed-off-by: Marc Zyngier <marc.zyng...@arm.com> Tested-by: Alex Bennée <alex.ben...@linaro.org> Reviewed-by: Alex Bennée <alex.ben...@linaro.org> Reviewed-by: Christoffer Dall <christ

[PATCH 08/31] arm64: KVM: Implement timer save/restore

Implement the timer save restore as a direct translation of the assembly code version. Signed-off-by: Marc Zyngier <marc.zyng...@arm.com> --- arch/arm64/kvm/hyp/Makefile | 1 + arch/arm64/kvm/hyp/hyp.h | 3 ++ arch/arm64/kvm/hyp/timer-sr.c

[PATCH 06/31] KVM: arm/arm64: vgic-v3: Make the LR indexing macro public

We store GICv3 LRs in reverse order so that the CPU can save/restore them in rever order as well (don't ask why, the design is crazy), and yet generate memory traffic that doesn't completely suck. We need this macro to be available to the C version of save/restore. Signed-off-by: Marc Zyngier

[PATCH 01/31] KVM: arm/arm64: vgic: make vgic_io_ops static

From: Jisheng Zhang vgic_io_ops is only referenced within vgic.c, so it can be declared static. Signed-off-by: Jisheng Zhang Signed-off-by: Christoffer Dall --- virt/kvm/arm/vgic.c | 2 +- 1 file changed, 1 insertion(+),

[PULL] KVM/ARM updates for 4.5

Amit Tomar (1): KVM: arm/arm64: Count guest exit due to various reasons Fengguang Wu (1): MAINTAINERS: add git URL for KVM/ARM Jisheng Zhang (1): KVM: arm/arm64: vgic: make vgic_io_ops static Marc Zyngier (23): arm64: KVM: Add a HYP-specific header file arm64: KVM

[PATCH 26/31] arm64: KVM: debug: Remove spurious inline attributes

lex Bennée <alex.ben...@linaro.org> Acked-by: Christoffer Dall <christoffer.d...@linaro.org> Signed-off-by: Marc Zyngier <marc.zyng...@arm.com> --- arch/arm64/kvm/sys_regs.c | 58 +++ 1 file changed, 29 insertions(+), 29 deletions(-)

[PATCH 29/31] arm64: KVM: Add support for 16-bit VMID

com> Signed-off-by: Marc Zyngier <marc.zyng...@arm.com> --- arch/arm/include/asm/kvm_arm.h | 2 +- arch/arm/include/asm/kvm_mmu.h | 5 + arch/arm/kvm/arm.c | 10 -- arch/arm64/include/asm/kvm_arm.h | 3 ++- arch/arm64/include/asm/kvm_mmu.h | 8 a

[PATCH 31/31] arm/arm64: KVM: Detect vGIC presence at runtime

d-by: Christoffer Dall <christoffer.d...@linaro.org> Signed-off-by: Marc Zyngier <marc.zyng...@arm.com> --- arch/arm/kvm/arm.c | 22 -- 1 file changed, 20 insertions(+), 2 deletions(-) diff --git a/arch/arm/kvm/arm.c b/arch/arm/kvm/arm.c index f6bcc2e..dda1959 100644 --- a/arc

[PATCH 27/31] arm/arm64: KVM: Remove unreferenced S2_PGD_ORDER

ff-by: Vladimir Murzin <vladimir.mur...@arm.com> Signed-off-by: Marc Zyngier <marc.zyng...@arm.com> --- arch/arm/include/asm/kvm_arm.h | 1 - arch/arm/kvm/mmu.c | 6 +++--- arch/arm64/include/asm/kvm_mmu.h | 1 - 3 files changed, 3 insertions(+), 5 deletions(-) diff --git

[PATCH 20/31] arm64: KVM: Map the kernel RO section into HYP

In order to run C code in HYP, we must make sure that the kernel's RO section is mapped into HYP (otherwise things break badly). Signed-off-by: Marc Zyngier <marc.zyng...@arm.com> Acked-by: Christoffer Dall <christoffer.d...@linaro.org> --- arch/arm/kvm/arm.c | 7 +++ 1 fil

[PATCH 24/31] arm64: KVM: Remove weak attributes

As we've now switched to the new world switch implementation, remove the weak attributes, as nobody is supposed to override it anymore. Acked-by: Christoffer Dall <christoffer.d...@linaro.org> Signed-off-by: Marc Zyngier <marc.zyng...@arm.com> --- arch/arm64/kvm/hyp/debug-sr.c | 5

[PATCH 28/31] arm: KVM: Make kvm_arm.h friendly to assembly code

places with it. Acked-by: Christoffer Dall <christoffer.d...@linaro.org> Signed-off-by: Vladimir Murzin <vladimir.mur...@arm.com> Signed-off-by: Marc Zyngier <marc.zyng...@arm.com> --- arch/arm/include/asm/kvm_arm.h | 33 + 1 file changed, 17 ins

[PATCH 30/31] MAINTAINERS: add git URL for KVM/ARM

From: Fengguang Wu <fengguang...@intel.com> Acked-by: Christoffer Dall <christoffer.d...@linaro.org> Signed-off-by: Fengguang Wu <fengguang...@intel.com> Signed-off-by: Marc Zyngier <marc.zyng...@arm.com> --- MAINTAINERS | 1 + 1 file changed, 1 insertion(+) di

[PATCH 23/31] arm64: KVM: Cleanup asm-offset.c

As we've now rewritten most of our code-base in C, most of the KVM-specific code in asm-offset.c is useless. Delete-time again! Signed-off-by: Marc Zyngier <marc.zyng...@arm.com> Acked-by: Christoffer Dall <christoffer.d...@linaro.org> --- arch/arm64/kernel/asm-of

[PATCH 2/2] arm64: KVM: Do not update PC if the trap handler has updated it

the access is performed, and checking if it has moved or not before incrementing it. Reported-by: Shannon Zhao <shannon.z...@linaro.org> Signed-off-by: Marc Zyngier <marc.zyng...@arm.com> --- arch/arm64/kvm/sys_regs.c | 73 +++ 1 file changed, 3

[PATCH 0/2] Fix PC corruption when injecting a fault

. The good news is that so far, we never do this, so I believe the current code is safe. But the PMU code is soon going to exercise that path, and I'd rather plug it sooner that later. Thanks, M. Marc Zyngier (2): arm: KVM: Do not update PC if the trap handler has updated it arm64: KVM: Do

[PATCH 1/2] arm: KVM: Do not update PC if the trap handler has updated it

the access is performed, and checking if it has moved or not before incrementing it. Reported-by: Shannon Zhao <shannon.z...@linaro.org> Signed-off-by: Marc Zyngier <marc.zyng...@arm.com> --- arch/arm/kvm/coproc.c | 14 -- 1 file changed, 12 insertions(+), 2 deletions(-)

Re: [PATCH v7] arm/arm64: KVM: Detect vGIC presence at runtime

On Fri, 18 Dec 2015 14:38:43 +0300 Pavel Fedin wrote: > Before commit 662d9715840aef44dcb573b0f9fab9e8319c868a > ("arm/arm64: KVM: Kill CONFIG_KVM_ARM_{VGIC,TIMER}") is was possible to > compile the kernel without vGIC and vTimer support. Commit message says > about

[PATCH] KVM: arm/arm64: vgic-new: Try to insert multi-source SGIs at once

Improve handling of multi-source SGIs: instead of only inserting one source per SGI per run, try to insert them all at once. Hopefully this is a rare case. Signed-off-by: Marc Zyngier <marc.zyng...@arm.com> --- virt/kvm/arm/vgic/vgic.c | 30 ++ 1 file chang

[PULL] KVM/ARM fixes for v4.4-rc6

Hi Paolo, We have a one line fix for the VGIC this time around, fixing a patch that went in -rc2. Oh well. Hopefully this is the last one for v4.4. Please pull! Thanks, M. The following changes since commit 0de58f852875a0f0dcfb120bb8433e4e73c7803b: ARM/arm64: KVM: correct PTE

Re: [PULL] KVM/ARM fixes for v4.4-rc6

Idiot alert, sending the wrong patch... On 18/12/15 13:00, Marc Zyngier wrote: > Hi Paolo, > > We have a one line fix for the VGIC this time around, fixing a patch > that went in -rc2. Oh well. Hopefully this is the last one for v4.4. > > Please pull! Or don't, actu

[PATCH] KVM: arm/arm64: vgic: Fix kvm_vgic_map_is_active's dist check

or, we first loop over the LRs but if not active in the LRs we just return if *any* IRQ is active on the VCPU in question. This is of course bogus, as we should check if the specific IRQ in quesiton is active on the distributor instead. Reported-by: Eric Auger <eric.au...@linaro.org> Acked-by:

[PULL take #2] KVM/ARM fixes for v4.4-rc6

Hi Paolo, We have a one line fix for the VGIC this time around, fixing a patch that went in -rc2. Oh well. Hopefully this is the last one for v4.4. And yes, the right patch is following the pull-request this time... Please pull! Thanks, M. The following changes since commit

Re: [PATCH v7 19/19] KVM: ARM64: Add a new kvm ARM PMU device

On Thu, 17 Dec 2015 15:22:50 +0800 Shannon Zhao wrote: > > > On 2015/12/17 4:33, Christoffer Dall wrote: > > On Wed, Dec 16, 2015 at 04:06:49PM +0800, Shannon Zhao wrote: > >> Hi, > >> > >> On 2015/12/16 15:31, Shannon Zhao wrote: > > But in this case, you're

Re: [PATCH v7 19/19] KVM: ARM64: Add a new kvm ARM PMU device

On 17/12/15 10:10, Shannon Zhao wrote: > > > On 2015/12/17 17:38, Marc Zyngier wrote: >> On 17/12/15 08:41, Shannon Zhao wrote: >>>> >>>> >>>> On 2015/12/17 16:33, Marc Zyngier wrote: >>>>>> On Thu, 17 Dec 201

Re: [PATCH v7 19/19] KVM: ARM64: Add a new kvm ARM PMU device

On 17/12/15 08:41, Shannon Zhao wrote: > > > On 2015/12/17 16:33, Marc Zyngier wrote: >> On Thu, 17 Dec 2015 15:22:50 +0800 >> Shannon Zhao <zhaoshengl...@huawei.com> wrote: >> >>>> >>>> >>>> On 2015/12/17 4:33, Christoffer

Re: [PATCH v7 07/19] KVM: ARM64: PMU: Add perf event map and introduce perf event creating function

On 17/12/15 15:22, Mark Rutland wrote: > On Tue, Dec 15, 2015 at 04:49:27PM +0800, Shannon Zhao wrote: >> From: Shannon Zhao >> >> When we use tools like perf on host, perf passes the event type and the >> id of this event type category to kernel, then kernel will map

Re: [PATCH] arm64: KVM: debug: Remove spurious inline attributes

On 17/12/15 16:28, Alex Bennée wrote: > > Marc Zyngier <marc.zyng...@arm.com> writes: > >> The debug trapping code is pretty heavy on the "inline" attribute, >> but most functions are actually referenced in the sysreg tables, >> making the inlining i

[PATCH] arm64: KVM: debug: Remove spurious inline attributes

lex Bennée <alex.ben...@linaro.org> Signed-off-by: Marc Zyngier <marc.zyng...@arm.com> --- arch/arm64/kvm/sys_regs.c | 58 +++ 1 file changed, 29 insertions(+), 29 deletions(-) diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c

Re: [PATCH v7 19/19] KVM: ARM64: Add a new kvm ARM PMU device

On 16/12/15 08:06, Shannon Zhao wrote: > Hi, > > On 2015/12/16 15:31, Shannon Zhao wrote: But in this case, you're returning an error if it is *not* initialized. I understand that in that case you cannot return an interrupt number (-1 would be weird), but

Re: [PATCH v7 15/19] KVM: ARM64: Add access handler for PMUSERENR register

On 15/12/15 15:59, Shannon Zhao wrote: > > > On 2015/12/15 22:58, Marc Zyngier wrote: >> On 15/12/15 08:49, Shannon Zhao wrote: >>>> From: Shannon Zhao<shannon.z...@linaro.org> >>>> >>>> The reset value of PMUSERENR_EL0 is UNKNOWN, use res

Re: ARM64/KVM: Bad page state in process iperf

On 15/12/15 03:46, Bhushan Bharat wrote: > > Hi All, > > I am running "iperf" in KVM guest on ARM64 machine and observing below crash. > > = > $iperf -c 3.3.3.3 -P 4 -t 0 -i 5 -w 90k > > Client connecting

Re: ARM64/KVM: Bad page state in process iperf

On 15/12/15 09:53, Bhushan Bharat wrote: > Hi Mark, > >> -Original Message----- >> From: Marc Zyngier [mailto:marc.zyng...@arm.com] >> Sent: Tuesday, December 15, 2015 3:05 PM >> To: Bhushan Bharat-R65777 <bharat.bhus...@freescale.com>; >> kvm...@

Re: ARM64/KVM: Bad page state in process iperf

On 15/12/15 10:57, Bhushan Bharat wrote: > > >> -Original Message----- >> From: Marc Zyngier [mailto:marc.zyng...@arm.com] >> Sent: Tuesday, December 15, 2015 3:50 PM >> To: Bhushan Bharat-R65777 <bharat.bhus...@freescale.com>; >> kvm...@lists.cs.co

Re: [PATCH v7 01/19] ARM64: Move PMU register related defines to asm/pmu.h

On 15/12/15 08:49, Shannon Zhao wrote: > From: Shannon Zhao > > To use the ARMv8 PMU related register defines from the KVM code, > we move the relevant definitions to asm/pmu.h header file. > > Signed-off-by: Anup Patel > Signed-off-by: Shannon

Re: [PATCH v7 19/19] KVM: ARM64: Add a new kvm ARM PMU device

On 15/12/15 15:50, Shannon Zhao wrote: > > > On 2015/12/15 23:33, Marc Zyngier wrote: >> On 15/12/15 08:49, Shannon Zhao wrote: >>>> From: Shannon Zhao<shannon.z...@linaro.org> >>>> >>>> Add a new kvm device type KVM_DEV_TYPE_

Re: [PATCH v7 08/19] KVM: ARM64: Add access handler for event typer register

On 15/12/15 08:49, Shannon Zhao wrote: > From: Shannon Zhao > > These kind of registers include PMEVTYPERn, PMCCFILTR and PMXEVTYPER > which is mapped to PMEVTYPERn or PMCCFILTR. > > The access handler translates all aarch32 register offsets to aarch64 > ones and uses

Re: [PATCH v7 11/19] KVM: ARM64: Add access handler for PMINTENSET and PMINTENCLR register

On 15/12/15 08:49, Shannon Zhao wrote: > From: Shannon Zhao > > Since the reset value of PMINTENSET and PMINTENCLR is UNKNOWN, use > reset_unknown for its reset handler. Add a handler to emulate writing > PMINTENSET or PMINTENCLR register. > > Signed-off-by: Shannon

Re: [PATCH v7 09/19] KVM: ARM64: Add access handler for event counter register

On 15/12/15 08:49, Shannon Zhao wrote: > From: Shannon Zhao > > These kind of registers include PMEVCNTRn, PMCCNTR and PMXEVCNTR which > is mapped to PMEVCNTRn. > > The access handler translates all aarch32 register offsets to aarch64 > ones and uses vcpu_sys_reg() to

Re: [PATCH v7 10/19] KVM: ARM64: Add access handler for PMCNTENSET and PMCNTENCLR register

On 15/12/15 08:49, Shannon Zhao wrote: > From: Shannon Zhao > > Since the reset value of PMCNTENSET and PMCNTENCLR is UNKNOWN, use > reset_unknown for its reset handler. Add a handler to emulate writing > PMCNTENSET or PMCNTENCLR register. > > When writing to

Re: [PATCH v7 13/19] KVM: ARM64: Add access handler for PMSWINC register

On 15/12/15 08:49, Shannon Zhao wrote: > From: Shannon Zhao > > Add access handler which emulates writing and reading PMSWINC > register and add support for creating software increment event. > > Signed-off-by: Shannon Zhao > --- >

Re: [PATCH v7 08/19] KVM: ARM64: Add access handler for event typer register

On 15/12/15 08:49, Shannon Zhao wrote: > From: Shannon Zhao > > These kind of registers include PMEVTYPERn, PMCCFILTR and PMXEVTYPER > which is mapped to PMEVTYPERn or PMCCFILTR. > > The access handler translates all aarch32 register offsets to aarch64 > ones and uses

Re: [PATCH v7 12/19] KVM: ARM64: Add access handler for PMOVSSET and PMOVSCLR register

On 15/12/15 08:49, Shannon Zhao wrote: > From: Shannon Zhao > > Since the reset value of PMOVSSET and PMOVSCLR is UNKNOWN, use > reset_unknown for its reset handler. Add a handler to emulate writing > PMOVSSET or PMOVSCLR register. > > When writing non-zero value to

Re: [PATCH v7 06/19] KVM: ARM64: Add access handler for PMCEID0 and PMCEID1 register

On 15/12/15 08:49, Shannon Zhao wrote: > From: Shannon Zhao > > Add access handler which gets host value of PMCEID0 or PMCEID1 when > guest access these registers. Writing action to PMCEID0 or PMCEID1 is > ignored. > > Signed-off-by: Shannon Zhao

Re: [PATCH v7 15/19] KVM: ARM64: Add access handler for PMUSERENR register

On 15/12/15 08:49, Shannon Zhao wrote: > From: Shannon Zhao > > The reset value of PMUSERENR_EL0 is UNKNOWN, use reset_unknown. > > PMUSERENR_EL0 holds some bits which decide whether PMU registers can be > accessed from EL0. Add some check helpers to handle the access

Re: [PATCH v7 16/19] KVM: ARM64: Add PMU overflow interrupt routing

On 15/12/15 08:49, Shannon Zhao wrote: > From: Shannon Zhao > > When calling perf_event_create_kernel_counter to create perf_event, > assign a overflow handler. Then when the perf event overflows, set the > corresponding bit of guest PMOVSSET register. If this counter is

Re: [PATCH v7 19/19] KVM: ARM64: Add a new kvm ARM PMU device

On 15/12/15 08:49, Shannon Zhao wrote: > From: Shannon Zhao > > Add a new kvm device type KVM_DEV_TYPE_ARM_PMU_V3 for ARM PMU. Implement > the kvm_device_ops for it. > > Signed-off-by: Shannon Zhao > --- >

Re: [PATCH v7 00/19] KVM: ARM64: Add guest PMU support

On 15/12/15 08:49, Shannon Zhao wrote: > From: Shannon Zhao > > This patchset adds guest PMU support for KVM on ARM64. It takes > trap-and-emulate approach. When guest wants to monitor one event, it > will be trapped by KVM and KVM will call perf_event API to create a

Re: [PATCH] KVM: arm/arm64: vgic: Fix kvm_vgic_map_is_active's dist check

> --- a/virt/kvm/arm/vgic.c > +++ b/virt/kvm/arm/vgic.c > @@ -1114,7 +1114,7 @@ bool kvm_vgic_map_is_active(struct kvm_vcpu *vcpu, > struct irq_phys_map *map) > return true; > } > > - return dist_active_irq(vcpu); > + return vgic

Re: [PATCH v3 07/22] arm64: KVM: Implement system register save/restore

Hi Mario, On 11/12/15 03:24, Mario Smarduch wrote: > Hi Marc, > > On 12/7/2015 2:53 AM, Marc Zyngier wrote: >> Implement the system register save/restore as a direct translation of >> the assembly code version. >> >> Signed-off-by: Marc Zyngier <marc.zyng...@

Re: [PATCH v6 10/21] KVM: ARM64: Add access handler for PMEVCNTRn and PMCCNTR register

Hi Shannon, On 10/12/15 11:36, Shannon Zhao wrote: > Hi Marc, > > On 2015/12/9 0:30, Marc Zyngier wrote: >> On 08/12/15 12:47, Shannon Zhao wrote: >>>> From: Shannon Zhao <shannon.z...@linaro.org> >>>> >>>> Since the reset value of PMEVCN

Re: [PATCH v6 07/21] KVM: ARM64: PMU: Add perf event map and introduce perf event creating function

On Wed, 9 Dec 2015 15:38:09 +0800 Shannon Zhao <zhaoshengl...@huawei.com> wrote: > > > On 2015/12/8 23:43, Marc Zyngier wrote: > > On 08/12/15 12:47, Shannon Zhao wrote: > >> From: Shannon Zhao <shannon.z...@linaro.org> > >> +/** > >>

Re: [PATCH v6 12/21] KVM: ARM64: Add reset and access handlers for PMCNTENSET and PMCNTENCLR register

On Wed, 9 Dec 2015 16:35:58 +0800 Shannon Zhao <zhaoshengl...@huawei.com> wrote: > > > On 2015/12/9 0:42, Marc Zyngier wrote: > >> +void kvm_pmu_enable_counter(struct kvm_vcpu *vcpu, u32 val, bool > >> all_enable) > >> > +{ > >> > +

Re: [PATCH v6 15/21] KVM: ARM64: Add reset and access handlers for PMUSERENR register

On Wed, 9 Dec 2015 17:18:02 +0800 Shannon Zhao <zhaoshengl...@huawei.com> wrote: > > > On 2015/12/9 1:03, Marc Zyngier wrote: > > On 08/12/15 12:47, Shannon Zhao wrote: > >> > From: Shannon Zhao <shannon.z...@linaro.org> > >> > >

Re: [PATCH v3 05/22] arm64: KVM: Implement vgic-v3 save/restore

On Mon, 7 Dec 2015 18:14:36 -0800 Mario Smarduch <m.smard...@samsung.com> wrote: > > > On 12/7/2015 10:20 AM, Marc Zyngier wrote: > > On 07/12/15 18:05, Mario Smarduch wrote: > >> > >> > >> On 12/7/2015 9:37 AM, Marc Zyngier wrote: >

Re: [PATCH v5 03/21] KVM: ARM64: Add offset defines for PMU registers

On 08/12/15 08:09, Shannon Zhao wrote: > Hi Marc, > > On 2015/12/7 22:55, Marc Zyngier wrote: >> On 07/12/15 14:31, Shannon Zhao wrote: >>>> >>>> >>>> On 2015/12/7 22:06, Marc Zyngier wrote: >>>>>> On 03/12/15 06:11, Sha

Re: [PATCH v3 06/22] arm64: KVM: Implement timer save/restore

On 08/12/15 02:18, Mario Smarduch wrote: > > > On 12/7/2015 2:53 AM, Marc Zyngier wrote: >> Implement the timer save restore as a direct translation of >> the assembly code version. >> >> Signed-off-by: Marc Zyngier <marc.zyng...@arm.com> >> ---

Re: [PATCH v6 02/21] KVM: ARM64: Define PMU data structure for each vcpu

On 08/12/15 13:53, Will Deacon wrote: > On Tue, Dec 08, 2015 at 01:37:14PM +0000, Marc Zyngier wrote: >> On 08/12/15 12:47, Shannon Zhao wrote: >>> From: Shannon Zhao <shannon.z...@linaro.org> >>> >>> Here we plan to support virtual PMU for guest by f

Re: [PATCH v6 06/21] KVM: ARM64: Add reset and access handlers for PMCEID0 and PMCEID1 register

On 08/12/15 12:47, Shannon Zhao wrote: > From: Shannon Zhao > > Add reset handler which gets host value of PMCEID0 or PMCEID1. Since > write action to PMCEID0 or PMCEID1 is ignored, add a new case for this. > > Signed-off-by: Shannon Zhao > ---

Re: [PATCH v6 02/21] KVM: ARM64: Define PMU data structure for each vcpu

On 08/12/15 12:47, Shannon Zhao wrote: > From: Shannon Zhao > > Here we plan to support virtual PMU for guest by full software > emulation, so define some basic structs and functions preparing for > futher steps. Define struct kvm_pmc for performance monitor counter and

Re: [PATCH v6 10/21] KVM: ARM64: Add access handler for PMEVCNTRn and PMCCNTR register

On 08/12/15 12:47, Shannon Zhao wrote: > From: Shannon Zhao > > Since the reset value of PMEVCNTRn or PMCCNTR is UNKNOWN, use > reset_unknown for its reset handler. Add access handler which emulates > writing and reading PMEVCNTRn or PMCCNTR register. When reading >

Re: [PATCH v6 07/21] KVM: ARM64: PMU: Add perf event map and introduce perf event creating function

On 08/12/15 12:47, Shannon Zhao wrote: > From: Shannon Zhao > > When we use tools like perf on host, perf passes the event type and the > id of this event type category to kernel, then kernel will map them to > hardware event number and write this number to PMU

Re: [PATCH v6 08/21] KVM: ARM64: Add access handler for PMEVTYPERn and PMCCFILTR register

On 08/12/15 12:47, Shannon Zhao wrote: > From: Shannon Zhao > > Add access handler which emulates writing and reading PMEVTYPERn or > PMCCFILTR register. When writing to PMEVTYPERn or PMCCFILTR, call > kvm_pmu_set_counter_event_type to create a perf_event for the

Re: [PATCH v6 12/21] KVM: ARM64: Add reset and access handlers for PMCNTENSET and PMCNTENCLR register

On 08/12/15 12:47, Shannon Zhao wrote: > From: Shannon Zhao > > Since the reset value of PMCNTENSET and PMCNTENCLR is UNKNOWN, use > reset_unknown for its reset handler. Add a new case to emulate writing > PMCNTENSET or PMCNTENCLR register. > > When writing to

Re: [PATCH v6 14/21] KVM: ARM64: Add reset and access handlers for PMOVSSET and PMOVSCLR register

On 08/12/15 12:47, Shannon Zhao wrote: > From: Shannon Zhao > > Since the reset value of PMOVSSET and PMOVSCLR is UNKNOWN, use > reset_unknown for its reset handler. Add a new case to emulate writing > PMOVSSET or PMOVSCLR register. > > When writing non-zero value to

Re: [PATCH v6 15/21] KVM: ARM64: Add reset and access handlers for PMUSERENR register

On 08/12/15 12:47, Shannon Zhao wrote: > From: Shannon Zhao > > The reset value of PMUSERENR_EL0 is UNKNOWN, use reset_unknown. > > Signed-off-by: Shannon Zhao > --- > arch/arm64/kvm/sys_regs.c | 5 +++-- > 1 file changed, 3 insertions(+), 2

Re: [PATCH v6 11/21] KVM: ARM64: Add access handler for PMXEVCNTR register

On 08/12/15 12:47, Shannon Zhao wrote: > From: Shannon Zhao > > Accessing PMXEVCNTR register is mapped to the PMEVCNTRn or PMCCNTR which > is selected by PMSELR. > > Signed-off-by: Shannon Zhao > --- > arch/arm64/kvm/sys_regs.c | 44

Re: [PATCH v6 18/21] KVM: ARM64: Add PMU overflow interrupt routing

On 08/12/15 12:47, Shannon Zhao wrote: > From: Shannon Zhao > > When calling perf_event_create_kernel_counter to create perf_event, > assign a overflow handler. Then when perf event overflows, call > kvm_vcpu_kick() to sync the interrupt. Please update the commit

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